The Design And Implemention Of External Memory Interface In FT-C55LP

In most embedded DSP-basing applications, on-chip memory is insufficient. Especially in digital image processing and audio processing, high speed and large capacity memory space is required to deal with large data stream. Therefore, DSP memory space needs to be extended by connecting external memory devices. Unfortunately, these memory chips have complex interfaces, which make them difficult to use.According to the requirement of extending FT-C55LP's memory space, an external memory interface is designed in this paper, which provides a glueless interface to three types of memory devices: asynchronous memory, SBSRAM and SDRAM. The on-chip devices access EMIF via system buses, and EMIF sends the request to corresponding memory chips according to the prescribed timing.Some key technologies are used in this design, such as asynchronous FIFOs, the fixed request priority arbitration based on circling token and the gradation of register address decoding. The design is composed of Bus interface, bus arbitration and RAM controller. Bus interface module regulates the protocol of EMIF and seven DSP system buses. Bus arbitration module defines the arithmetic of bus arbitration. RAM controller module implements asynchronous memory controller, SBSRAM controller and SDRAM controller. In the design, principles of high speed and low power are displayed.Register transfer level verification is carried out. In the verification, bottom-up policy is adopted. On the base of built platform, industrial memory Verilog soft cores are connected with EMIF. The module, device and system level function verification are done. The result shows that the designed EMIF is correct in function and has high compatibility, meeting the design requirement.Finally, because the power of memory occupies a greater and greater portion of power in embedded systems, the technique of power reduction is proposed in this paper. Write / read merging and monitoring bus utilization dynamically technologies are used. Theoretic analysis is done on the proposed method.