Design Of High-Resolution Panoramic Images Real Time Processing Hardware System Based On DSP And FPGA

Because high-resolution panoramic images in real time processing system to obtain a 360 degree horizontal and vertical range of high-definition 180-degree scene images, so more and more attention and more and more widely used. The traditional system is based on common low-resolution video images of ordinary sensors, the field is small, only tens of degrees of the observed field of view. Panoramic imaging systems is the use of the catadioptric optical imaging, and by high-performance image processing hardware and software systems are panoramic images clear and stable, while the technology has been applied to robot navigation, video surveillance and many other fields.Because the system uses high-resolution CCD imaging, image resolution and frame rate are high, on the requirements and image processing system is more and more high, it is generally difficult to meet the general-purpose processor to high-resolution real-time processing Requirements.In this paper, high resolution panoramic images of the collection, cache, and display the output of solving real problems were studied. Because the system requires high resolution and high frame rate, resulting in very high data rates, and the algorithm must be given sufficient time for solving the problem, this article on how to achieve such high resolution and multi-processor parallel processing system Structure was analyzed. At the same time how to implement this system, an overall design, and separately from the functional requirements, the overall structure of the program the hardware, software, programs and other aspects of the structure were analyzed and, ultimately, a high performance DSP and FPGA formed a multi-processor Parallel systems. FPGA to complete the acquisition of image data, cache, display and various control logic functions; through the design of highly efficient 64-bit SDRAM controller to complete a burst read and write buffer control; FPGA for ping-pong buffer operation for the entire system High-speed cache, to ensure coordination of DSP and FPGA in parallel; the image data transmitted by FPGA, through the EMIF interface and the way of DMA, then DSP receive data to complete the process of solving a variety of algorithms; DSP's EMIF interface to re-use of data transmitted through the DMA, back to the FPGA; then FPGA cached the data to the cache device, the last sent to the monitor. The design for the circuit, PCB design and debug, and PCB reliability was studied through the system software and hardware co-debugging, real-time parallel processing system to achieve the requirements of high resolution The test results show that the system can accomplish real-time panoramic image acquisition, buffering and resolving with 2048x2048 15fps based on camera Link interface. The system also can accomplish real-time display out with 1024 x 768.