Design Of DDR2 SDRAM Controller Based On FPGA

With the constant reduction of IC process geometries, the integration density of SoC is increasingly high, and the operating frequency of CPU and storage has become double increased, resulting in a higher demand for transferring and processing large data streams rapidly. As the exchange bridge between the microprocessor and the memory, the memory controller has always been one of the most important factors that constrains the performance of the entire computer system. Therefore, a high-performance and high-efficiency memory controller is the core bond exploiting the performance limit of microprocessors and memories.Based on the design of an actual project, the researches of this paper were conducted to complete the design and FPGA implementation of a DDR2 SDRAM controller. This controller was designed and implemented to complete initialization, refreshing, read and write calibration, read latency minimization of DDR2 SDRAM. A special data strobe (DQS) clock gating circuit was adopted to avoid clipped pulse width and glitch noise of the DQS clock. Furthermore, dynamic phase shift circuits were exploited to tackle the delay mismatch between data signal (DQ) and DQ, DQ and DQS, a Delay-locked loop circuit (DLL) being utilized to compensate the timing effects caused by Process/Voltage/Temperature (PVT) changes. The establishment of the fuction verification platform, Pre-synthesis simulation and FPGA verifcation were accomplished by using such EDA tools as Modelsim and Quartus II. DDR2 SDRAM operated at 400MHz, while the frequency of the DDR2 SDRAM controller was reduced to the half,200MHz, to facilitate the development of the DDR2 SDRAM controller. The results of simulation and FPGA verification manifested that when DDR2 SDRAM operated 400MHz, the maximum read latency was only 60ns, good stability and reliability being achievedThis DDR2 SDRAM controller IP can be integrated into SoC for high-speed accesses to DDR2 SDRAM devices. In addition, SDRAMs’ development from SDR, through DDR and DDR2, to DDR3, has been being concentrated on the capacity, the frequency, lower voltages, the prefetching architecture and power consumptions, which causes the fact that all these generative SDRAMs have a great inheritance and similarity on the operation timing. Consequently, research results of this paper have a good reference value for the design of DDR3 controller and the futural DDR4 controller.