Design Of Interface With FIFO Features To Control DDR/DDR2 SDRAM

In order to meet the requirement of high-capacity and high-speed storage medium in electronics, DDR SDRAM has been used more and more, and it needs better interface and more convenient way to use. In this paper, building a modular system is an effective way. It has been used in some projects of ZTE Beijing Corporation.This article first introduces the background of the topics, including domestic and foreign related research, then introduces the principle and the development process of DDR SDRAM and interface, and analyzes its position and function in the system. Then article introduces the implementation of FIFO character based on Stratix-II GX FPGA, and analyzes the main unit, data entry and data cache unit. Through the software platform chipscope, on-line debugging works for analyzing problems and summarizing some technology issues and solutions.Through the development and debugging of this system, I realize a transmission character with FIFO feature, and make a convenient interface to the complexity of the timing of high-capacity, high-speed storage medium applications.