Research On Several Influencing Factors Of Single Event Transient In Bulk FinFET Devices

With the rapid development of China's space technology,the radiation mechanisms and the design of radiation-hardened integrated circuits(ICs)have become the main concerns in academia and industry.However,in nanometer scales,the device size and the supply voltage continue to shrink,while the clock frequency increases dramatically,which result in the SET-induced soft error becoming the key factor of rad-hardened performance in nano ICs.As a result,with the Fin FET technology has gradually become the mainstream process of the more advanced nano scale CMOS ICs,the research on the SET of Fin FET devices and circuits have been unavoided.In the Fin FET process,the device structure has changed significantly,which has an important influence on the mechanism of SET.On the one hand,the introduction of fin structure makes the contact area between the drain region and the substrate greatly reduced,which makes the Fin FET devices exhibit a natural resistance to single event effects compared to planar devices;on the other hand,the structure change of Fin FET devices has an important influence on the single event charge collection,which makes the SET mechanism in Fin FET devices more complex.In addition,the size and space of the devices are further reduced under the nano Fin FET process;thus the effect of the charge sharing on the single event charge collection and the generation of SET is more obvious.Therefore,based on the different relationships between adjacent nodes in Fin FET circuits,we can use the charge sharing positively to enhance the SET pulse quenching effect;also we can suppress the single event multiple transient(SEMT)effect by reducing the charge sharing.Based on the new characteristics of the SET in nano bulk silicon Fin FET devices,the main works and contributions of this dissertation are as follows:(1)The SET sensitivity of nano silicon Fin FET and conventional planar devices was compared in depth.Based on 28-nm bulk-Si Fin FETs and planar transistors,three-dimensional technology computer-aided design(TCAD)simulations are performed to investigate the charge collection mechanisms and single-event transient(SET)pulse widths for nanoscale devices.Simulation results show that charge collection and SET pulse widths for Fin FETs are smaller than those of the planar device.An overall analysis indicates that for P-hits,the reduced charge collection in p-Fin FET is induced mainly by the narrow sensitivity drain volumes when ion linear energy transfer(LETs)less than 20 Me V-cm2/mg;however,the parasitic bipolar amplification effect presents an important effect on the charge reduction for higher ion LETs.An in-depth analysis shows that the reduced bipolar amplification effect in p-Fin FET is owing to the conduction channel(fin body)rather than source/drain region.Due to a parasitic reversed bipolar effect,the single-event response for N-hit is less sensitive than that for P-hit.Moreover,comparisons of the temperature dependence of SET pulse width in both Fin FETs and planar devices is carried out,which indicate that the SET pulse width in PMOS shows stronger temperature dependence than that in p-Fin FET.(2)It was found that the change of fin structure has a significant effect on the single event charge collection and SET pulse width of Fin FET devices,and the narrow/ multi fin devices have better anti SET characteristics.Based on a 28-nm bulk Fin FET device,we have investigated the fin width and height dependence of bipolar amplification for heavy ion irradiated Fin FETs by 3-D TCAD numerical simulation.Simulation results show that due to a well bipolar conduction mechanism rather than a channel(fin)conduction path,the transistors with narrower-fin exhibit diminished bipolar amplification effect,while the fin height presents a trivial effect on the bipolar amplification and charge collection.The results also indicate that the single event transient(SET)pulse width can be mitigated about 35% at least by optimizing the ratio of fin width and height,which can provide guidance for radiation-hardened applications in bulk Fin FET technology.In addition,the change of fin number can directly affect the sensitive drain area of the device,and the Fin FET devices with more fin number will exibit stronger single event resistance.(3)An effective body-biasing scheme was presented to enhance the SET pulse quenching effect in Fin FET devices.Using three-dimensional 3-D technology computer aided design(3DTCAD)mixed-mode simulations,the effects of voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk Fin FET process.Research results indicate that due to an enhanced charge sharing effect,the propagating SET pulse width decreases with reducing supply voltage.Moreover,compared with reverse body-biasing(RBB),the circuit with forward body-biasing(FBB)is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least.(4)It is found that the SEMT effect of Fin FET devices can be effectively suppressed under the SDDS layout..Research results show that due to the isolation of the STI region in the SDDS layout structure,the charge sharing effect of the 16-nm bulk Fin FET devices is greatly reduced and the SEMT effect of is effectively suppressed.Also the results show that the charge sharing and the SEMT effect of the Fin FET process are weaker than that of the planar process.(5)A chip was designed to test the SET of different inverter circuit units based on 16 nm bulk Fin FET process.This test chip consists of multiple inverter modules.Through the radiation experiments,we can have a more comprehensive understanding of the SET characteristics of the Fin FET standard cell.Moreover,we can verify the SET pulse quenching effect and the SEMT effect in the Fin FET process from theBased on the fact that the SET has become the main source of the soft errors in the advanced Fin FET integrated circuits,this paper studies in depth the mechanism and effect of SET in Fin FET device and circuit.The influence of the structural parameters of the Fin FET device and the voltage/temperature changes on the SET pulse width was studied and some new characteristics of SET in Fin FET process were revealed.Thus a more systematic understanding of the SET characteristics of Fin FET devices was formed,which can provide raw data for SET hardened design in the future Fin FET devices and circuits;Also can provide theoretical guidance for the design of anti radiation reinforcement of integrated circuit in the bulk silicon Fin FET process.