Research And Optimization Of 24-bit Sigma Delta ADC System Structure Based On MASH Structure

With the continuous development of digital signal processing technology,the analog-to-digital converter is attracting more and more attention.With different application scenarios,different types of ADCs have been developed.Such as: high-speed ADC,high-resolution ADC,etc.With the rapid development of audio,precision instruments and other fields,Sigma Delta ADC has developed rapidly and has been applied in related fields due to its high resolution.Sigma Delta ADC mainly consists of two parts: one is Sigma Delta modulator adapting oversampling technology and noise shaping technology;the other is digital decimation filter.This article first compares modulators of different structures,and confirms that the structure of modulator in this article is a feed-forward MASH structure.Then the structure of a traditional feed-forward MASH2-2 modulator is analyzed,and its shortcomings are summarized,and a new feed-forward MASH2-2 structure is proposed.The improved MASH2-2 structure modulator was simulated in MATLAB and Cadence respectively.In order to obtain a high-resolution modulator structure,a feed-forward MASH2-1-1structure modulator is further analyzed,and system parameters are further optimized on the basis of the original parameters.Build model simulations in MATLAB and Cadence respectively.The results show that when the signal sampling frequency is 4.096 MHz,the signal frequency is 4KHz,and the oversampling rate is 128 times,the MASH2-1-1structure modulator can more easily achieve a high signal-to-noise ratio.Then use the verilog A model in Cadence to model and simulate fully differential switched capacitor circuit of MASH2-1-1 structure modulator,and import the modulator output into MATLAB to calculate its signal-to-noise ratio and effective number of bits;Digital decimation filter used as another component of Sigma Delta ADC is formed by CIC filter with a recursive structure and halfband filter with an equal ripple design method.Digital decimation filter is designed,analyzed and modeled in MATLAB,and hardware description language is written in Xilinx ISE to implement it.The simulation results show that modulator of MASH2-1-1 structure can reach the effective number of 24 bits;CIC filter can achieve 32 times downsampling,halfband filter can achieve 4 times downsampling,and digital decimation filter can achieve 128 times decimation of sampling frequency of modulator.