Design Of A High-precision Sigma-Delta ADC Modulator

Nowadays,the Internet,AI,sensors,and 5G communication technologies are developing rapidly.The advanced digital circuit field needs the same high-performance analog parts to match them.As an analog-to-digital converter(ADC)as a bridge between the analog and digital worlds,high-precision Sigma-Delta ADCs have become a research hotspot.However,at present,the domestic research system for high-precision Sigma-Delta modulators is not complete,and the circuit structure is highly restrictive.Therefore,this paper designs a high-precision Sigma-Delta modulator structure,and studies the optimization accuracy from two aspects in view of the above problems.Modulator accuracy is improved by modeling behavioral levels of non-ideal factors.The process of non-ideal factor modeling and simulation can more accurately design the parameters of the actual circuit.In order to improve the modeling effectiveness,this paper adds a non-ideal factor model that has a large impact on the circuit based on the basic modulator model that has been considered for pole-zero optimization.Using the Simulink tool of MATLAB,the The overall modulator model was modeled at the behavioral level and the design program selected various parameter values in the model and simulated for FFT analysis.Based on this,the parameter design and optimization of the system are performed to obtain a higher-precision,closer to the actual modulator behavior-level model.Improve the accuracy of the modulator by optimizing the structure of the circuit module.In order to improve the accuracy of circuit conversion,an improved feed-forward fourth-order modulator is designed in this paper.The Sigma-Delta modulator in this design uses a single-loop CIFF(Cascade of Integrators Feedforword)feedforward cascade structure with high tolerance for device mismatch.It consists of a fourth-order integrator and a one-bit quantizer.Differential structure to optimize system performance.Due to the structural characteristics,the output swing is small and the stability is high.The design of each sub-module in the circuit has been carefully analyzed and considered.Compared with the traditional Sigma-Delta modulator structure,it has been optimized and improved.The switched capacitor integration circuit adopts a hierarchical design for the integrator.The structure of the first-stage integrator is different from the latter three-stage integrator.Chopping technology is added to the first-stage integrator to reduce noise;in order to improve the resolution and regeneration time,a band is used.Pre-amplifier regenerative comparator structure;in order to reduce the influence of non-ideal factors of the switch,two-phase non-overlapping clock control is designed to achieve different working states.The Sigma-Delta modulator can achieve a signal-to-noise-to-distortion ratio of about 118 d B in a behavior-level modeling simulation,with about 20 effective digits.The whole circuit is simulated and verified on the Cadence platform using a 0.18?m CMOS process and a power supply voltage of 5V.The input signal bandwidth is 2KHz.When the OSR is 256,a resolution of about 18 bits can be achieved.This design can meet the design requirements of high precision,and is suitable for application areas with low signal bandwidth.Due to its high accuracy,it has a wide range of application areas.