Study And Design Of High-resolution Sigma-delta ADC

The research of high resolution, low power analog-to-digital converters is one of the most popular problems in recent years. By adopting oversampling technique, noise shaping and digital filtering, sigma-delta analog-to-digital converter(Σ-ΔADC) has stood out from the other ADCs which could decrease the requirements of the analog circuits design and achieve very high resolutions. However, the sigma-delta technique has a drawback that it cannot conduct very high sampling rate. TheΣ-ΔADC will therefore face the challenge of high speed, high resolution and low power consumption.The characteristics of ADC which introduce the performance of the system is very important. There are two categories of the characteristics: dynamic performances, such as signal-to-noise-ratio, spurious-free-dynamic-range, and static performances, such as integral-nonlinearity and differential- nonlinearity. The paper has made a systemic introduction of these characteristics and demonstrated them.TheΣ-ΔADC consists mainly of the analog modulator and the digital filter. This paper makes a deep analysis on the systematic design of the whole ADC by using Matlab and summarizes a complete design method. According to the sampling rate, resolution and the dynamic characteristics, the feed-forward factors, feedback factors and the gain factors of the integrators can be established. Then, the performance of the modulator can be predicted by using Matlab.The non-idealities of the analog circuits could dramatically decrease the performance of the modulator. It is necessary therefore, to make a systematic and quantized analysis of these non-idealities. The non-idealities include finite dc gain of the operation amplifier, finite unity-gain-bandwidth, finite slew rate, saturation, non-linearity of sampling switch, jittering, KT/C noise and so on.TheΣ-Δmodulator in this paper adopts 2-order single-loop multi-bit architecture and accompanies with the factors of feedback and feed-forward, the modulator achieves a high resolution. 4-bit quantizer is used to reduce the quantization noise. A novel bootstrapped switch with clock feed-through compensation technique is used to reduce the harmonic distortion and therefore improves the dynamic performance of the converter. Since the sigma-delta ADC has a narrow bandwidth, the gain of the operational amplifier is important. In this design, the operational amplifier adopts two-level architecture: first level is a cascaded structure and the second is a common source level. The common mode feedback is realized by switch-capacitor circuits which could increase the output swing range of the operational amplifier. The comparators in the 4-bit quantizer adopt an improved class-AB latched comparator which could theoretically and practically decrease the kickback noise. The comparator has the advantages of high sensitivity and low power and much lower kickback noise.Since non-linearity introduced by multi-bit quantizer influences the performance of the system seriously, digital calibration method is used to suppress the effects of this noise. Among dynamic element matching techniques, data weighted averaging technique is the simplest and practical. Data weighted averaging technique makes the quantization noise white which could improve its dynamic performance and would not increase the power consumption and area dramatically. Proper adoption of the sampling capacitors and integral capacitors will help to reducing chip area and power consumption. A high-resolution band-gap reference provides the voltage and current for the circuits. The use of the non-overlap clocks reduces the system noise introduced by the clock error.The filter behind the analog modulator is realized by all CMOS technology which makes the power and area the challenges of the design. In this paper, a digital decimation filter of bandwidth of 21.77kHz and a sampling frequency of 6.144MHz, decimation rate of 32 is designed. Firstly, system design is done on the basis of theoretical analysis. Each stage is optimized and compared with the traditional ones after the multi-stage architecture is determined. Then, analysis on coefficients and bit-width of the filter is analyzed in detail when the hardware circuits are realized. Consists with multi-stage, the filter has a much lower power and smaller area than the one implemented by only one stage. The final simulation results show that the designed filter meets the requirements of the converter. The sampling rate reduced to Nyquist rate after the digital filter which makes the need of storage and calculation requirements relax for the later digital signal procession.The proposed second-order 4-bitΣ-ΔADC is designed in Chartered CMOS 0.35μm technology. All measurement results were taken with a 5V analog and 5V digital power supply. The ADC achieves 102.8dB dynamic range over a 24kHz bandwidth. The core die area, which includes the reference voltage circuit and decimation filter is 13.4mm2.Power consumption is less then 180mW. ENOB(Effective-Number-of-Bit) of the modulator is higher than 16.8-bit. The expected objective is achieved.