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Study And Implement Of Low-power Two-order Sigma-delta ADC

Posted on:2014-01-18Degree:MasterType:Thesis
Country:ChinaCandidate:G J WangFull Text:PDF
GTID:2268330422950085Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The research of high performance analog-to-digital converters is one of the most populardiscussion points in integrated circuit analog design domain. By adopting noise shaping anddigital filtering, over-sampling technique, sigma-delta ADC has been widely used in digitalaudio, digital Network and digital measurement systems. The sigma-delta modulationmechanism could decrease the quantization noise of the bandwidth and the over-samplingmechanism could increase the SNR and therefore increase the resolution of the converters.Consisted with analog modulator and digital decimation filter, the sigma-delta ADC hasa resolution which is determined by the performance of the noise shaping. This paper makes adeep analysis on the systematic design of the whole ADC by using MATLAB. According tothe sampling rate and resolution, the feed-forward factors, feedback factors and the gainfactors of the integrators can be established. Then, the performance of the modulator can bepredicted by using MATLAB. Besides, making a systematic and quantized analysis of thesenon-idealities, including finite dc gain of the operation amplifier, finite unit gain bandwidth,finite slew rate, saturation, non-linearity of sampling switch, jittering, kT/C noise and so on,then simulated the non-ideal modulator by using MATLAB, which provide the basis forsubsequent circuit design.It studies the process information of the BCD offered by the foundry at first. This paperpresents an over sampled two-order single-loop single-bit sigma-delta analog-to-digitalconverter followed by a multi-stage decimation filter. The modulator in this work is a fullydifferential circuit that operates from a single2.7-V power supply. The digital filter is athree-order CIC filter. The circuit is designed and simulated with Spectre, the program andmodel file is provided by the foundry. Design details and measurement results of the wholechip are presented for a HHNEC0.18μm BCD implementation to achieve an ENOB of12.21-b performance over a baseband of4kHz.The simulation result and the test data showsthat the specification of the design are met, which satisfy the design requirements. The validity of the theoretical analysis and the practicality of the design are proved.
Keywords/Search Tags:analog-to-digital converter, Sigma-delta modulator, SNR, Switched-capacitor, Digital decimation filter
PDF Full Text Request
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