Design And Study Of High-performance Sigma-delta ADC

The research of high performance, low power analog-to-digital converters (ADC) is one of the most popular discussion points in microelectronic analog design domain. By adopting oversampling technique, noise shaping and digital filtering, sigma-delta ADC has been widely used in digital audio, ISDN (Integrated Services Digital Network) and digital telephone systems. The sigma-delta modulation mechanism could decrease the quantization noise in the bandwidth and the oversampling mechanism could increase the SNR (Signal-to-Noise-Rate) and therefore increase the resolution of the converters.Consisted with analog modulator and digital decimation filter, the sigma-delta ADC has a resolution which is determined by the performance of the noise shaping. This paper makes a deep analysis on the systematic design of the whole ADC by using MATLAB and summarizes a complete design method. According to the sampling rate, resolution and the dynamic characteristics, the feed-forward factors, feedback factors and the gain factors of the integrators can be established. Then, the performance of the modulator can be predicted by using MATLAB. The non-idealities of the analog circuits could dramatically decrease the performance of the modulator. It is necessary therefore, to make a systematic and quantized analysis of these non-idealities. The non-idealities include finite dc gain of the operation amplifier, finite unit gain bandwidth, finite slew rate, saturation, non-linearity of sampling switch, jittering, KT/C noise and so on.There are mainly two types architecure belong to sigma-delta ADC:Single-loop and MASH (Multi-stAge-noise-SHaping), and they have their own advantages and disadvantages. Therefore, a high-order single-loop multi-bit sigma-delta modulator and a MASH24b-24b have been designed in this paper.Generally speaking, the high-order single-loop sigma-delta modulator is popular in many applications such as systems which require high SNR ADC, simple analog circuits design and nice distortion performance. Although, multi-bit quantizer can ensure the stability of the modulator since the quantization noise is decreased, one-bit quantizer has the advantage of inherent linearity. When the requirement of high linearity is needed, one-bit quantizer is widely used in these systems. This paper presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital converter followed by a multi-stage decimation filter. Design details and measurement results of the whole chip are presented for a TSMC0.18μm CMOS implementation to achieve an ENOB of15.31-b performance over a baseband of640kHz. The modulator in this work is a fully differential circuit that operates from a single1.8-V power supply. With an oversampling ratio of64and a clock rate of81.92MHz, the modulator achieves a94dB dynamic range. The decimator achieves a pass-band ripple of less than0.01dB, a stop-band attenuation of80dB and a transition band from640kHz to740kHz. The whole chip consumes only56mW for a1.28MHz output rate and occupies a die area of1mm×2mm. Since the decimation filter is implemented in all CMOS circuits, the main problem is area and power dissipation. Designed in a cascaded structure, the storage and calculation of the decimator can be decreased and simplified. The sampling rate after filtered by the decimation becomes Nyquist rate. The layout is important as well since the chip includes not only analog circuits but also digital circuits which could influence the performance of the analog part.However, there is a main disadvantage in sigma-delta ADC:low speed or low bandwidth. Therefore, high speed, high resolution and low power for the one modulator are the main problems in the future. An improved low distortion sigma-delta ADC for WLAN (Wireless Local Area Network) standards is presented in this paper. A feed-forward MASH24b-24b multi-bit cascaded sigma-delta ADC is adopted. However, this work has a much better performance than the ADCs which had been presented up to date by adding a feedback factor in the second stage to improve the performance of in-band SNDR (Signal-to-Noise-and-Distortion-Ratio), using4-bit ADCs in both stages to minimize the quantization noise and, therefore, DWA(Data Weighted Averaging) technology is used to decrease the mismatch noise induced by the4-bit DACs which improves the SFDR of the ADC. The modulator has been implemented by a0.18μm CMOS process and operates at a single1.8V supply voltage. Experimental results show that:for a-6dBFS@1.25MHz input signal at160MHz sampling frequency, the improved ADC with all non-idealities being considered achieves a peak SNDR of80.9dB and a SFDR of87dB. the ENOB (Effective-Number-of-bit) is13.15-bit.