Design And Study Of Fully Differential Four Order Sigma-delta Modulator

Owing to the oversampling and noise shaping, the high resolution can be easily achieved by sigma-delta ADC compared with the conventional ADC. With the research of sigma-delta ADC to be further, higher resolution, lower power consumption and higher sampling frequency become the focus of study. Nowadays, sigma-delta ADC is widely applied to the measuring detection system, digital audio and communications. Sigma-delta ADC can be divided into sigma-delta modulator and digital filter. Under this circumstance, a high resolution sigma-delta modulator is proposed for the measuring detection system.A signal loop four order one bit structure is adopted in the design of modulator to reduce the nonlinear quantization and improve the whole performance. Based on the system design method to be presented, using the DSToolbox tools in the MATLAB, the behavioral simulation of the whole modulator is completed. The simulation shows the SNDR of the whole modulator is 112 dB. At the same time, the non-idealities in the behavioral simulation are quantized as the performance requirements in the design of the circuits. The whole circuit is design in Cadence IC simulation environment with the GSMC 130 nm CMOS process. To reduce the even order distortions, power consumption and nonlinearity, the modulator is built in the fully differential switch capacitor circuit. With the power supply is 3.3V, the sampling frequency is 1MHz and the input is-4.4BFS in 1KHz, simulation result shows that the SNDR and ENOB of modulator is 107 dB and 17.6bit, which means the high performance of the modulator is succeed. Finally, the layout of the modulator is also realized.