Research On High-order Discrete-time Multi-bit Sigma-Delta Modulator Technology

With the advent of 5G technology,signal processing technology has developed rapidly.As an important component of signal processing,analog-to-digital converter(ADC)has received extensive attention.At present,the development trend of ADC is high speed,high precision and low power consumption.Among them,Sigma-Delta ADC is widely used in high-precision products such as audio,biological,and pressure sensors due to its unique working principle.Compared to continuous-time Sigma-Delta modulators,discrete-time sensitivity to mismatch is low,and is often used in low-frequency applications.Therefore,combined with the application background of the sensor,this paper is devoted to the research of low-power and high-precision Sigma-Delta modulator,and selects 20 KHz signal bandwidth and 100 dB SNR as the design goals of discrete-time Sigma-Delta modulator.In order to reduce the power consumption of the modulator,this article selects the SAR ADC quantized discrete time Sigma-Delta modulator.This design firstly determines the order and structure of the modulator through calculation according to the design index.Then,through the Simulink model,the noise transfer function of the modulator is calculated,and the relationship between the integral gain coefficient and the feedforward coefficient is determined.Through the coefficient scaling,the modulator coefficient is mapped into the circuit-level design.This paper uses a feed-forward MASH structure to achieve the performance of the 4th order Sigma-Delta modulator,ensuring the stability of the modulator.By comparing different 4th order MASH structures,the modulator chooses MASH 2-2 structure to achieve.Then the Simulink modeling and analysis of the non-ideal factors in the modulator were carried out,and the FFT results of the modulator with non-ideal factors were obtained.Based on the modeling of non-ideal modulators,the modulators are designed at the circuit level,mainly including the design and optimization of modules such as integrators,comparators,clock generation circuits,multi-bit quantizers,and DWA circuits.Using 4-bit SAR ADC as the quantizer,the switching timing of SAR ADC,gate voltage bootstrap switch,unit capacitance selection,comparator,SAR control logic,etc.were analyzed and discussed.In order to eliminate the mismatch introduced by the multi-bit DAC,the DWA circuit is connected after the SAR quantizer,and the DAC unit is selected by rotation to achieve the average of the mismatch in the case of large data to ensure the performance of the modulator.The SMIC 0.18 process was used to complete the design of the SAR quantized MASH 2-2 structure discrete-time Sigma-Delta modulator.The previous simulation showed that under the target bandwidth,the SNDR was 109.6dB,the effective number of bits was 17.92 bits,and the power consumption was 4.63 m W,which satisfied the design aims.Through Simulink modeling in MATLAB,the digital elimination logic of the modulator and the digital decimation filter were modeled,designed and analyzed.The digital elimination logic is based on the principle of the MASH structure modulator,and the elimination module and its coefficients are accurately designed so that the final output contains only the quantization noise of the last sub-modulator.The digital decimation filter adopts the cascade structure of CIC filter,CIC compensation filter and half-band filter,which realizes 32 times decimation and reduces the design cost.Due to its simple structure and single coefficient,the CIC filter is used in the first stage to achieve a large decimation rate.The second stage uses a CIC compensation filter to compensate the 1.1 dB pass-band roll-off of the CIC filter.After the compensation,the pass-band roll-off is less than 0.01 dB,and the extraction is performed twice.Finally,use a half-band filter to achieve 2 times decimation and filtering.FFT analysis of the system-level design shows that the input frequency of the digital decimation filter is 4MHz.After the three-stage filter,the output frequency is 125 KHz,the transition band bandwidth is 85 KHz,and the passband roll-off is limited to 0.01 dB The number of digits is 17.67,which meets the design goals.