Design And Research Of HV LDMOS Based On Electric Field Modulation

As a typical power device,the lateral double-diffused metal-oxide-semiconductor field effect transistor(LDMOS)has been widely used in automotive electronics,power management,driving circuit of lighting and other fields due to the easy integration of its coplanar electrodes.Throughout the development history of LDMOS,the higher breakdown voltage(BV)and lower specific on-resistance(R_on,sp)are always our purpose.However,BV and R_on,sp are a pair of contradictory electrical properties,for example,the increase of BV is usually accompanied by the increase of R_on,sp.So far,a variety of theories and technologies have been put forward to alleviate this phenomenon by many domestic and overseas scholars,such as the field plate technology,the superjunction technology,the reduced surface field(RESURF)technology and the linear doping technology.The essense of these methods is to increase the breakdown voltage of LDMOS without changing the specific on-resistance remarkably by modulating the internal electric field distribution.Based on the concept of electric field modulation,two new LDMOS devices are designed by optimizing the two-dimensional device structure and three-dimensional layout,respectively.The electric field distribution and physical mechanisms of the two new devices are investigated in detail by Sentaurus simulations.Furthermore,the devices are verified by process design,layout drawing and electrical measurements.The main contents of this thesis can be summarized as follows.Firstly,a Segmented Triple-RESURF LDMOS(SETR LDMOS)with segmented P-buried layer is proposed.The device divides the single P buried layer near the drain side in the drift region of traditional Triple-RESURF LDMOS(TR LDMOS)into an evenly spaced structure with multiple P buried layers.On one hand,when the BV of device is determined by the lateral withstand voltage,the segmented P buried layer structure can effectively prevent the N-well depletion caused by the excessively high P type concentration on the drain side of LDMOS in the blocking state,reducing the peak electric field on the surface of the drain side.At the same time,the strong substrate assisted depletion effect caused by the substrate at the bottom of the drain can be suppressed,and the charge distribution in the blocking state can be further optimized,achieveing the optimal effect of electric field modulation.On the other hand,the segmented P buried layer structure can increase the curvature radius of the vertical PN junction,optimizing the vertical electric field distribution and significantly improving the vertical withstand voltage of LDMOS.The optimal parameter structure of the device is obtained by the actual fabrication and tests.Test results show that the BV of the SETR LDMOS can reach 813 V,about 6.69%higher than that of the conventional TR LDMOS(about 762 V)with the same drift region length of 63?m,while keeping the specific on-resistance unchanged(about 7.3?·mm²).Secondly,a novel terminal-optimized Triple-RESURF LDMOS(TOTR LDMOS)is proposed by replacing part of Deep N-well region in the drift region with low doping P--region.This treatment can not only alleviate the strong electric field phenomenon caused by the low curvature radius of reverse biased junction in the terminal region,but also transform from the abrupt voltage junction to a graded junction,effectively improving the BV in the terminal region and exhibiting good performance of the straight part(the main working area of the device).Sentaurus simulations show that the optimized TOTR LDMOS has a flatter electric field distribution in the terminal region and a significantly suppressed peak electric field on the drain side.Compared with the traditional TR LDMOS,it significantly improves the breakdown problem in the terminal region.The devices are fabricated,and the test results show that the BV of TOTR LDMOS can reach 817 V,about 8%higher than that of traditional TR LDMOS(about 775 V).Furthermore,the optimization of the terminal region have no effect on the low specific on-resistance of 6.99?·mm² since the terminal region does not provide a current path when the device is operating normally.In summary,the two new high-voltage LDMOS devices can show excellent performance in 700 V control circuits.