Research On High Voltage Field Control Power Devices And Integration Technology In 700V BCD Process

700V BCD process has been widely used in power management, motor driver, automotive electronics and industrial control. Compared with traditional “two in one”(Controller + Discrete device) pattern, it is cheaper to manufacture, easier to package, more convenient to design and with less external devices. High voltage switch devices and start-up devices are the most important devices in 700 V BCD process. Pursuing smaller Ron,sp(specific on-resistance) and higher BVDS(Breakdown Voltage between Drain and Source) are the main development direction of the 700 V switch LDMOS(Lateral Double-diffused MOS). RESURF(REduce SURface electrical Field) technology such as Double RESURF and Triple RESURF are the main technologies to reduce the Ron,sp of LDMOS. JFET(Junction Field-Effect Transistor) is one of the most common start-up devices. Pursuing less VP(pinch-off voltage of JFET), smaller DIBL(Drain Induced Barrier Lowering) effect and high BV are the main development direction of high voltage JFET.Main innovations of this thesis are: Firstly, a 700 V dual conducton paths with Dual p-Buried layers n-type LDMOS(DB-n LDMOS) is proposed. It contains: an analytical model for Rdson, an optimized technology for Ron,sp and a high voltage self-isolated technology. Secondly, a 700 V low pinch-off voltage n type JFET is proposed. It contains an optimized technology for lower VP and smaller DIBL effect of JFET. This thesis including:Firstly, using 0.35 μm technology and ion implantation technology, a 700 V DB-n LDMOS is proposed. It contains a NISO(source None-ISOlated) DB-n LDMOS and a ISO(source ISOlated) DB-n LDMOS. Firstly, an analytical model for Ron(on resistance) of LDMOS is given to find the optimization direction of Ron,sp and BVDS. Secondly, an optimized technology which includes two aspects is used to reducing Ron,sp. On the one hand, the thermal budgets after Pbury layer implantation are strictly limited, then low Ron,sp with large process torlerance are achieved. On the other hand, sizes of neck region of devices are optimized to achieve low Ron,sp. Experimental results show that Ron,sp of NISO DB-n LDMOS and ISO DB-n LDMOS are 11.5 ?·mm2 and 11.2 ?·mm2 respectively. The BVDS are 800 V and 780 V respectively. These results are superior to most of other exising technologies. Thirdly, by separately implanting two DNW(deep NWELL) regions, a self-ISO DB-n LDMOS is realized. High BVDS is achieved due to low-concentration DNW in the neck region which avoids the concentration of the electric field under bird’s beak.Secondly, a 700V n JFET with low VP is proposed, it contains a Dual p-Buried layers n JFET(DB-n JFET) and a Thin Channel Triple RESURF n JFET(TCT-n JFET). Compared with traditional structures, both these two n JFET have lower VP, smaller DIBL effect, high BV and large ID,sat(saturation current). These advantages are benefit from optimized technologies as follows: Firstly, p type layers are introduced in JFET channel region. For channel current, the control ability of VGS is increased which brings low VP and small DIBL effect. Secondly, high BV is benefit from Triple RESURF technology and junction terminal technology. Experimental results show that: for DB-n JFET, when VD equals 500 V, VP is 30 V with 2.6 m A – ID,sat, SDIBL(DIBL sensitivity) is only 5.7%. For TCT-n JFET, VP is 24 V with 2.3 m A – ID,sat, SDIBL is only 3.5%. In adition, both two JFETs achieve 800 V OFF-BV(OFF-state BV) and 650 V ON-BV(ON-state BV). In addition, a low-cost and low-power high voltage startup circuit with 40 V p JFET and 700 V n JFET is also proposed in this part. Compard with traditional circuit, it saves large layout area due to dependent 700 V n JFET and 40 V p JFET which can limit the current to a stable low value with small device layout area.Thirdly, a Dual conduction paths Segmented Anode Lateral Insulated-Gate Bpolar Transistor(DSA-LIGBT) which uses triple RESURF technology is proposed. Due to hybrid structures of triple RESURF LDMOS(T-LDMOS) and traditional LIGBT, firstly, wide p-type anode is benefit to the small shift voltage(VST) and low Ron,sp when anode voltage(VA) is larger than VST. Secondly, wide n-type anode and triple RESURF technology are used to get low Ron,sp when VA is less than VST. Meanwhile, it can accelerate the extract of electron which brings small turn-off time(Toff). Experimental results show that: VST is only 0.9 V. Ron,sp are 11.7 ?·mm2 and 3.6 ?·mm2 when anode voltage VA equals 0.9 V and 3 V, respectively. Breakdown voltage reaches to 800 V. Toff is only 180 ns.Lastly, integrating power devices mentioned before, a 0.35 μm 700 V BCD platform is proposed. The main advantages are: firstly, 700 V n LDMOS has low Ron,sp of only 11.7 ?·mm2 with 800 V- BVDS, which can significantly reduce the chip area. Secondly, high productivity is achieved with simple steps and low mask layers. Thirdly, it is low-cost and easy to manufacture without any specific process or material. Fourthly, it features high integration density due to 0.35 μm process technology and small device size. Lastly, it has high reliability and high yield which are verified by both wafer-level and product-level experiments.