Research For A LDMOS With Low Specific On-Resistance And Its Terminal Structure

In modern times,almost every electronic device in every home uses direct current,but what we get from the power plant through the transmission line is alternating current,because alternating current is a more convenient and energy saving method of transmission than direct current.Therefore,every appliance operating in the DC state requires a conversion circuit to convert alternating to direct current.LDMOS?Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor?often appear in AC/DC conversion circuits in the role of low-side switching high voltage integrated power supply devices.As a power switch tube,LDMOS devices need to be able to withstand high voltage when in the off state,and have small switching loss and power loss when in the on state.This means that LDMOS cannot blindly increase the breakdown voltage of the device by increasing the voltage region length of the device.This will increase the device area and increase the loss of the circuit system at the same time,which is in contradiction with the miniaturization required by the high voltage integrated circuit.Therefore,increasing the BV of LDMOS while reducing the R_on,sp of the device are always the main efforts of scholars in relevant fields.In this thesis,an N-P-N LDMOS with low R_on,sp is proposed.Based on the conventional Triple RESURF LDMOS,two N-doped layers are added into the drift region,to the surface of the drift zone and below the p-buried layer,respectively.This will introduce more majority carriers into the device so that when the device is on,the conduction resistance in the current path from the drain to the source will reduce.Since the reduction of the conduction resistance is not completely dependent on the n-type layer on the surface,the problem of high surface electric field caused by the high concentration of N-type layer on the surface can be avoided,which brings better reliability to the device.Firstly,for the proposed N-P-N LDMOS,based on a high-voltage integrated process platform,this thesis formulates a process flow matching with N-P-N LDMOS.In addition,this thesis models the functional relationship between the BV of N-P-N LDMOS and R_on,sp under ideal conditions:R_on,sp=5.93×10^-6×18.6×BV²,?=18.6.Compared with the traditional Triple RESURF technique?=32,the proposed N-P-N LDMOS apparently achieves a lower R_on,sp under the same BV,which theoretically demonstrates that the new structure performs well in the BV and R_on,sp relationships.Secondly,in order to obtain the optimal performance of BV and R_on,sp,this thesis simulated and optimized the design of N-P-N LDMOS device in detail.The optimization direction is mainly as follows:?1?Straight region's optimization.Because the N-P-N LDMOS adopts local oxidation isolation technology,there is a beak region.In order to avoid the beak effect,this thesis carries out the optimized design of the beak region of the device.In addition,due to the proposed N-P-N LDMOS compared with the conventional Triple RESURF LDMOS,the innovation lies in the introduction of N-P-N layer in the drifting region.Therefore,this thesis use the Tsuprem 4 software to optimize the key process parameters such as implantion dose and implantion energy of each layer of N-P-N to obtain the optimal BV and R_on,sp of this structure.?2?Terminal region'optimization,the terminal structure in the layout is divided into terminal area and transition area,and the key parameters of transition area are optimized in detail,so that the peak electric field of device breakdown falls in the straight area.Finally,this thesis carried out the flow plate experiment on the N-P-N LDMOS in the cooperation company,and took the EMMI photo of the device after the breakdown,which showed that the breakdown position of the device fell on the straight area instead of the terminal area,thus achieving the goal of terminal optimization.The final experimental results show that the breakdown voltage of N-P-N LDMOS is 795V and R_on,sp is 78.3 m?·cm².Comparing with results of other devices,we found that the proposed N-P-N LDMOS device performs well in reducing power loss.