Research On High Voltage RESURF LDMOS With Field Plate Technology And High Voltage Interconnection

Generally, high side and low side integrated on one chip in high voltage power integrated circuit sometimes, and in order to achieve this high voltage power integrated circuit, a high breakdown voltage device is needed. High voltage LDMOS is adopted for high voltage power integrated circuit which used as switching transistor to satisfy the current and the voltage demand. In order to realise this function, HVI(High Voltage Interconnection) metal line, extended from the drain contact of LDMOS for transferring low voltage logic signal to high voltage control part will be introduced, and HVI is the most important issue in high voltage power IC. HVI metal line, extending from the high side of power devices, causes severe local electric field crowding because the high electric potential of interconnection affects the electric field distribution of silicon surface. This brings much lower breakdown voltage(BV) than expected BV for LDMOS. To avoid the breakdown voltage reduction, thick insulating film technology, field reduction layer technology, field plate technology and self-shielding technology have been proposed previously. The four kinds of HVI technologies prevent BV degradation from the introduced adverse charge induced by interconnections in different ways. Among those four kinds technology, field plates have a significant effect for the optimization of device surface electric field, the number and the length of field plates have great influence on the BV of device, and field plates can reduce the peak of electric field.1. high voltage LDMOS and RESURF technologyThe breakdown voltage of the LDMOS in this thesis needs to achieve 600 V at least. The relationship between epitaxial concentration and P-top dosage that need to satisfy the RESURF requirement has been studied by using the simulation software Silvaco. RESURF technology can improve the BV of device by transfer the surface breakdown to inner breakdown.2. HVI(high voltage interconnection) and termination structureThrough the research on the device terminal structure, the influence of HVI to the BV of device can be reduced, and the model of HVI has been analysed. High voltage interconnection is a key factor to deteriorate the blocking performance of high voltage power integrated circuit. Thick insulting film technology, field reduction layer technology, field plate technology, self-shielding technology can reduce the influence of HVI to device. Thick insulting film technology can reduce the influence of HVI to the device mainly through increasing the distance between the HVI and surface of silicon. Field reduction layer technology uses additional doping layers with optimized impurity concentration to enhance the depletion of the drift region under HVI to reduce the influence of HVI to the device. Field plate technology is mainly through optimizing the surface potential and electric field distribution of device to reduce the influence of HVI to the device. Self-shielding technology has avoiding HVI crossing over the surface of device, so no additional shielding structure is needed to reduce the influence of HVI to the device.3. High voltage power LDMOS with floating field plateField plate technology needs no additional process. Single layer floating field plate can use poly-silicon to achieve, and same process with gate. This thesis mainly studied the relationships among the epitaxial concentration, the dose of P-top layer and field plate, and the research on field plate mainly include the number, spacing and the length of field plate. Finally, the process steps and the layout of devices have been given out.