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Design Of Novel Low Specific On-resistance LDMOS With Trench Gate

Posted on:2022-04-20Degree:MasterType:Thesis
Country:ChinaCandidate:L YangFull Text:PDF
GTID:2518306740493874Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
The LDMOS(Lateral Double-Diffusion Metal Oxide Semicionductor,LDMOS)transisitor is widely used in power integrated circuits due to its high breakdown voltage,excellent high frequency performance and easy integration.In recent years,the rapid rise of high-tech promote the further development of LDMOS in the direction of high performance.However,the on-resistance of traditional bulk silicon LDMOS cannot meet requirements of application systems due to the existence of silicon limit.The trench gate structure can extend the current path to the inside of the device which can reduce the on-resistance,so it is of great significance to study the trench gate LDMOS.In this thesis,a novel LDMOS device with low on-resistance is designed which adopts the combination of trench gate and planar gate.Firstly,in order to solve the unequal threshold voltage of the double gates,the process flow is improved and the angled N-type impurity implantation is adopted to ensure that the double gates are turned on at the same time to achieve low on-resistance.Then,based on the simulation software,the simulation model of the device is established.It focuses on optimization of trench gate,planar gate and metal field plate to get best device structure that meets the design specifications.Finally,the reliability of the device was studied,the results show that adding an N-buffer at the drain can suppress the Kirk effect and the conduction of the parasitic NPN transistor,thereby improving the electrostatic discharge reliability and widening the safe oprating area;Under the worst stress condition,the main damage point of the device is the"bird's beak"under the planar gate.Using segmented linear doping in the N-drift can effectively reduce the current density here and improve the reliability of hot carriers.The final simulation results show that the threshold voltage of the novel low specific on-resistance LDMOS with trench gate is 1.30V,the breakdown voltage is 44.03V,the specific on-resistance is 10.65m??mm2,the on-state breakdown voltage is 35.3V,and the secondary breakdown current is 2.42?10-3A/?m,the peak value of impact ionization ratio under the worst stress is6.22?1027cm-3/s,which meets the design specifications and achieves a good balance between breakdown voltage,specific on-resistance and reliability.
Keywords/Search Tags:lateral double-diffused metal oxide semiconductor(LDMOS), trench gate, specific onresistance, breakdown voltage, reliability
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