Design And Simulation Of Novel Low Voltage LDMOS Structures

LDMOS(Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor) has been a key device for the achievement of the PIC(Power Integrated Circuit) mainly due to the feature that its gate, source and drain are on the same side of the chip surface and it is easy to realize the integration with the low voltage signal compared with VDMOS(Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor). The main demand of the PIC is low power, which is corresponding to the low specific on resistance and the high breakdown voltage in LDMOS. Nowadays, the main domestic and foreign research focus is on applying new materials, new processes and new structures to optimize these two demands. The structures and performances of two novel lateral double-diffused power devices are analyzed and optimized with specific emphasis on novel structures. A brief description of the process is also included in this paper.First of all, the paper reported a novel device named New Folding Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor with Step Oxide(SOFLDMOS): Firstly, the conductive region of gate is increased by the folding structure in order to reduce the specific on resistance, the principle of which is similar to the Fin FET(Fin Field-Effect Transistor); Secondly, the electron accumulation layers in drift region are caused by the extension of the gate electrode in the step oxide, which can also decrease the specific on resistance of the drift region, what is more, the electron accumulation layers are formed in the side wall of the drift region I to reduce the specific on resistance because of the folding structure; Thirdly, the concentration of drift region is increased by the electric field modulation effect of X and Y directions on the off station in order to decrease the specific on resistance; Lastly, a new electric field peak is introduced in the lateral electric field distribution to optimize the surface electric field by the electric field modulation effect of the step oxide; The influence of various parameters on device performance is analyzed by simulation software in this paper, the proposed SOFLDMOS shows that the specific on resistance of 0.32 m?.cm~2 with the breakdown voltage of 62 V, which is decreased by about 63% compared the specific on resistance of 2m?.cm~2 with the same breakdown voltage in the conventional LDMOS.Then, the paper reported a novel device named New SJ-LDMOS with the P-type Covered Layer(P covered SJ-LDMOS): The novel structure is based on the existing N buffered super junction LDMOS, the difference of the proposed structure is that the P-type covered layer is partly above the N-type of the super junction layer. The problem of the substrate-assisted depletion which is caused due to the P-type substrate of the N-channel SJ-LDMOS is eliminated by completely compensating for the charges between the N-type buffered layer and the P-type covered layer, thus increasing the breakdown voltage; what is more, the concentration of the N-type buffered layer is improved by the effect of charge compensation of P-type covered layer which can reduce the specific on resistance of the device. The results of the ISE software suggest that when the drift region is in a scale of 10?m, the proposed structure shows that the specific on resistance of 4.26m?.cm~2 with the breakdown voltage 203 V, which is decreased by about 59% compared with the specific on resistance of 10.47m?.cm~2 in the conventional SJ-LDMOS, and decreased by about 43% compared with the specific on resistance of 7.46m?.cm~2 in the N Buffered SJ-LDMOS.Lastly, the processes of the SOFLDMOS and the P covered SJ-LDMOS are designed. The process difficulty and the method to solve that are also reported in this paper.