Design Of 40 V Thin Film SOI LDMOS

With the development of modern power integration technology,lateral double-diffused metal oxide semiconductor field effect transistor(LDMOS)has been widely used in power integrated circuits because of its high breakdown voltage and high driving current.However,with the increasing demand of power integrated circuits for LDMOS performance,the specific on-resistance of traditional bulk silicon LDMOS cannot be further reduced due to the existence of silicon limit.Silicon on insulator(SOI)technology uses a buried oxide(BOX)between the top silicon and the substrat.Due to the strong voltage withstand ability of the oxide,it creates space for further reducing the specific on resistance of LDMOS.Therefore,it is of great significance to study SOI LDMOS.In this thesis,40 V thin film SOI LDMOS is designed.Firstly,based on the simulation software of technology computer aided design(TCAD),the simulation model of the device is established.Then,the top silicon and buried oxygen layer thickness,field plate structure,injection dose in N-well and drift region are designed.It is found that the breakdown voltage of the device can be significantly increased by using thin oxide layer and top silicon.The breakdown voltage can also be further increased by the source plate structure.The ideal compromise between the breakdown voltage and the specific on-resistance can be achieved by using the appropriate drift concentration.After that,the reliability of the device is studied.Under the worst stress condition,the hot electron injection at field oxide and the end of source plate will cause serious linear drain current degradation.Properly changing the length of source plate can inhibit the hot carrier injection effect.It is found that the Kirk effect and the parasitic transistor will make the maintenance voltage and the on-state breakdown voltage low.Adding an N-buffer to the drain of the device can widen the safe oprating area and optimize the electrostatic discharge response curve.According to the structure design and reliability research of the device,the final structure and process parameters are determined.After that,the tapeout and wafer test are carried out.The tapeout results show that the threshold voltage is 1.28 V,the breakdown voltage is 59.17 V,the specific on-resistance is 20.15 m??mm²,the on-state breakdown voltage is 44 V,the maximum degradation of threshold voltage under the worst stress condition is1.98%,the maximum degradation of specific on-resistance is 9.77%,and the secondary breakdown current under the transmission line pulse(TLP)test is 2.17×10^-3 A/?m.It is shown that the tapeout results achieve the expected targets.