The Structure Design And Simulation Of High-voltage SOI LDMOS

In the rapid development of society,the high voltage integrated circuit is widely used in various fields,and LDMOS in high voltage integrated circuit design is the first choice for high voltage circuit.In order to meet the requirements of high voltage integrated circuit,the development of semiconductor technology continuously,and for the high voltage LDMOS device,its requirements is more stringent.In high voltage integrated circuit design process,the size of LDMOS is reduced,and the breakdown voltage of the device will not be reduced or even larger.In order to meet this requirement,the structure design and material were considered.This paper mainly discusses how to improve the breakdown voltage of LDMOS devices in the LDMOS device structure design.Due to the SOI LDMOS device performance is much better than bulk silicon LDMOS device,so this paper focuses on the SOI LDMOS device.In this paper,it firstly introduces the SOI technology and its preparation method.And then introduces the design method of the SOI LDMOS device.Finally,in the design of SOI LDMOS devices,some design parameters must be attented,such as: the field plate,the channel region,the drift region and the buried oxide layer.After knowing how to design the LDMOS SOI devices with excellent performance,a lateral double-diffused MOSFET with double oxide trenches in silicon-on-insulator(SOI)technology is presented(DOT SOI LDMOS).The oxide trenches can cause multiple-directional depletion in the drift region.This can reshape electric field distribution and improve the reduced surface field effect(RESURF).Laterally,the top oxide trench can increase the electric field due to the low permittivity,which enhances the lateral breakdown voltage(BV).In the vertical direction,the bottom oxide trench can prevent holes being swept away,which improves the electric field in the buried oxide layer(BOX)and thus vertical breakdown voltage.Consequently,breakdown voltage is improved.through 2-D simulations by Sentaurus TCAD,the results show that the BV of DOT LDMOS increases from 359 V of the conventional SOI LDMOS to 470 V.Another kind of LDMOS SOI device structure is proposed in this paper.High-voltage lateral double-diffused MOSFETs with two(P/N)types of partial buried silicon layer(PBPL/PBNL)are investigated numerically in Silicon-on-Insulator(SOI)technology for comparison(PBNL/PBNL SOI LDMOS).In the lateral direction,the partial buried silicon layer(PBL)can introduce an additional electric field peak,which improves the surface electric field distribution and increases the charge accommodation in the drift region.Consequently,in the vertical direction,PBPL and PBNL can both induce higher electric field into the BOX layer,and thus enhance the breakdown voltage(BV)significantly.Due to the higher electron concentration in the drift region,the on-resistance(Ron)can be also reduced remarkably.The 2-D simulation results show that PBPL and PBNL SOIs can achieve 296 V and 365 V,respectively,in comparison to the conventional SOI(225V)and the BNL SOI(231V).Compared with CSOI,Rons are reduced by about 31.7% and 13.8% for PBPL and PBNL SOIs,respectively.