Design Of 40V Thin SOI PLDMOS

P-type Lateral Double Diffused Metal-oxide-Semiconductor（pLDMOS）,as the core device that can simplify the complexity of power integrated circuits and reduce the chip area,has the problems of high on-resistance and high power dissipation in practical application.Based on the advantages of thin Silicon-On-Insulator（SOI）devices,such as uniform vertical electric field distribution,low on-resistance and high reliability,a thin SOI-pLDMOS device with low on-resistance,high voltage withstand and high reliability is designed.In the thesis,a 40V thin SOI pLDMOS device is designed by using the Computer-Aided Design software.Firstly,in order to effectively reduce the vertical electric field peak and improve the vertical breakdown voltage of the device in off-state,the thickness of top silicon,the thickness of buried-oxide layer and the impurity concentration in the HV-nwell zone are designed.By designing the impurity injection window,injection energy and injection dose in the P-drift region,the internal impact ionization and potential distribution are changed,so that the breakdown voltage and on-resistance of the device are compromised.Furthmore,n-well region,polysilicon field plate and source metal field plate are designed to optimize the surface electric field strength and current path of the device.Based the design of device,the reliability of the device is studied in the thesis.Under the conditions of maximum substrate current and maximum gate voltage,studying shows that the degradation of threshold voltage is small due to less hot hole injection in channel region,the on-resistance decreases is large due to large amount of hot electron injection in drift region.Additionaly,studying shows that 40V thin SOI-based pLDMOS devices barely exist snapback phenomenon,resulting in excellent Electro-Static Discharge（ESD）robustness of the device.The experimental results show that the threshold voltage,breakdown voltage and characteristic on-resistance of the 40V thin SOI-based pLDMOS device are-1.25V,-52V and 69.2 mΩ?mm²respectively.The degradation of threshold voltage under the two maximum stress conditions is less than 2%and the on-resistance decreases by about 9%,the secondary breakdown current is 6.7911×10^-2A/μm,and the DC and AC open breakdown voltage of the device is greater than 1.1 times of the working voltage,which all satisfy the requirements.