Design Of 14Bit Low Power Consumption Capacitive SAR ADC

With the development of society,people need to deal with more and more information.Digital signal processing technology provides a powerful tool for people to enter the era of big data.Analog to Digital Converters(ADC)is the key module to convert Analog signals to Digital signals.Successive Approximation ADC(Successive Approximation Register ADC,SAR ADC)with simple structure,low power consumption and good growth potential in many structures,become a hotspot of research on AD converter,widely used in various types of mobile devices and medical equipment.In this paper,based on the detailed introduction and analysis of the principle of SAR ADC,a 10 bit synchronous timing sequence SAR ADC is designed by using 180 nm process,and a 14 bit asynchronous timing sequence SAR ADC is designed by improving on this basis.The capacitance array of the traditional charge-type SAR ADC follows a power superposition of 2,and the overall area increases exponentially with the increase of accuracy.In this paper,the piecewise capacitance structure is used to divide the whole capacitance array into two parts,LSB and MSB,to reduce the overall capacitance area.In addition,redundant bits are added to the capacitance array of the MSB segment to reduce the impact of ADC error codes.Through the comparison of synchronous timing and asynchronous timing structure,the asynchronous timing structure built by TSPC module is finally chosen,and the switching process is improved.Compared with the traditional lower plate capacitor switching mode,the area of the whole capacitor array is reduced by half.With the sampling rate of 5MS/s,the effective bit is 13.5 bits,SNDR83.03 d B,and the quality factor is 20.7fj /conversion-step.The final design of 14 bit SAR ADC achieves good performance.