Design Of 10-bits C_R Succesive Approximation Register Analog-to-digital Converter

With the development of electronic and information technology, wireless communication technology is widely used in many fields. The high frequency signal processed through low noise amplifier, mixer, filter, was converted to digital signals for subsequent processing.As the bridge between analog signals and digital signals, a high-performance Analog to Digital Converter(ADC) module is crucial.The circuit mentioned in paper is a successive approximation analog-to-digital conversion with 10 precision, 1 MS/s conversion speed and low power consumption. We used a hybrid circuit structure, that is capacitors combine with resistances, to build the DAC module of the ADC. The ADC circuit can be used in the field of RF wireless carrier communication.We chosen the C-R hybrid circuit structure, according to the parameter of usual ADC structure includes low power consumption, high precision, small area. In the six most significant bit we used charge scaling and the four low significant bit used voltage scaling. In order to be more effective against noise and interference, the ADC circuit uses whole symmetrical difference structure. In the LSB, we used a progressive structure instead of three-eight decoder and thermometer-coded, to reduce the impact on the accuracy of the number of switches. In addition, in order to reduce power consumption, we only used one resistor string.On the differential input of comparator, two samples voltage are alternately applied. The core of successive approximation logic is the binary search algorithm, it can controls the corresponding switch opening and closing based on results of the comparator output, and complete the voltage successive approximation. The comparator output encoding, after the digital logic processing, as the output code of the ADC module.The main modules of the circuit including the DAC module(chapter 3), the comparator(chapter 4), sample/hold circuit, the reference voltage buffer(chapter 5), digital control part(chapter 6), they constitute these modules such as switching circuit, environment matching capacitance and resistance together to the whole circuit.Through the design and simulation, we completed a hybrid 10 bits SAR ADC from front-end to back-end. The circuit is in 0.18?m process, the working frequency is 16 MHz,the input frequency is from 1Hz to 500 KHz, the conversion speed is 1MS/s. In Pre-Simulation, DNL=±0.2LSB, INL=±0.5LSB. With the input frequency 200 KHz, SNR=60.88 d B, SNDR=60.55 d B, ENOB=9.77 bits. Furthermore the static power consumption is 42.15?W, dynamic power consumption is 0.79 m W, layout area is 0.17625mm2. In Post-Simulation, ENOB=8.83 bits. The circuit can convert differential signal, which come from Filter or PGA, into 10 bits digital coding.