Hardware Design And Implementation Of Low-latency Turbo Code Decoding Algorithm

Turbo code is a kind of channel coding based on parallel concatenated convolutional code.It has become one of the channel coding standards of CCSDS because of its excellent performance in anti-fading and anti-interference.Based on this standard,this paper implements the hardware design and implementation of Turbo codec with frame length of 8160.Firstly,the principle of turbo coding and decoding is introduced briefly.Then its performance is simulated,and the hardware design and improvement method are studied.Finally,the actual performance of Turbo code is tested in the project system.In the simulation of MATLAB,this paper analyzes the performance of three decoding algorithms.Through the comparison of different parameter angles,the basic performance indexes of 8160 frame turbo code are obtained,and the results are compared with the relevant literature.Aiming at the shortcomings of traditional MAP decoding algorithm,such as large delay and low throughput,an improved decoding structure based on the Sliding-window Max-log-map-algorithm is proposed in FPGA hardware design.The improvements mainly includes the following four points.The first point is to adopt the design method of two component decoder parallel decoding.The second is to split the calculation structure of branch metrics.The third point is to design component decoder 1 and 2 independently,which are combined with the newly designed interleaver and deinterleaver.The fourth point is to use pipeline structure to complete the "comparison and selection" calculation,and optimize the storage and reading methods of prior information.Through the above improvements,the decoding delay time is reduced,the throughput is increased and the resource consumption is reduced.Compared with the traditional decoding structure,the LLR output time of the single component decoder is 99% earlier and the memory resource of the decoder is 67% saved.The test on the system platform of the project shows that the designed turbo decoder can work stably under the clock of 130 MHz.The turbo codec implemented in this paper has been successfully applied to a real-time image data transmission system of UAV.The delay time of decoder is less than 5ms,and the throughput is higher than 8mbps when iterating 5 times,which meets the requirements of image data transmission in this project.