Design Of Turbo Decoder In MIMO-GMC System And Its FPGA Implementation

Turbo code is a new family of convolutional codes. It is based on concatenated code, MAP algorithm, SISO(soft-in-soft-out) algorithm and iterative decoding. Turbo encoder is built from a parallel concatenation of two recursive systematic codes, linked together by nonuniform interleaving. Its decoder is characterized by an iterative process in which each component decoder takes advantages of the work of the other at the previous step. Investigated by simulation, the error correcting performance of turbo codes with sufficient large interleaving sizes appears to be close to the theoretical limit shown by Shannon.FPGA (Field Programmable Gate Array), developed from programmable logic devices such as PAL, GAL, EPLD, etc. With its advantages like large scale, high integration, high dependability, short design period, small investment, high flexibility, the FPGA technology has become an ideal choice of complex IC design.Under the back of the MIMO-GMC wireless transmission technology proposed by B3G group in National Communication Research Laboratory (NCRL) of Southeast University, this dissertation analyzes the decoding algorithms of Turbo code. According to the External Information Reserved approach and the joint iteration of detection and decoding used by the iterative receiver of the MIMO-GMC system, the design of the SISO (soft-in-soft-out) Turbo decoder using SW-Log-MAP algorithm is completed in this dissertation. The whole design is finished in Verilog HDL, and finally implemented on a Virtex II Pro device.