Research On Decoding Tech Of Convolutional Turbo Codes

The thesis is about convolutional turbo codes(CTC) constructed via parallel concatenation of two circular recursive systematic convolutional(CRSC) encoder linked by an interleaver. Convolutianal Turbo codes are very flexible codes, easily adaptable to a large range of data block sizes and coding rates. This is the main reason for their being adopted in the WiMAX system.First, this thesis presents the theoretical background of channel coding and turbo coding and introduces the encoding structure of CTC. Then, a general and efficient maximum a posteriori(MAP) soft-input soft-output(SISO) decoding algorithm is presented. And then, the simplified Max-Log-MAP algorithm is derived for CTC. For circular trellis structure of CTC, whatever elementary algorithm is used, iterative decoding requires repeated turns around the circular trellis(es), iterations naturally follow one after the other without any discontinuity between transitions from state to state. For both forward and backward process, probabilities computed at the end of a turn are used as the initial values for the next turn, which could improve the decoder performance. The thesis also presents the simulation results under different algorithms and parameters.Then, the FPGA design and implementation of CTC decoder is detailed. The decoder has a parallel sub-block decoding and pipeline structure to achieve high throughput. The decoder adopts sliding window algorithm to reduce the decoding delay. The decoder divides the data into several subblocks and deals with them separately, which could reduce the time delay of MAP algorithm. The most important module (StateUpdate) in the design is optimized by'module algorithm'. The Verilog design of the decoder is implemented on the FPGA chip (Xilinx Virtex II Vp70). Finally, the thesis draws concludes and points out future research directions.