An All Digital Phase Locked Loop For Image Sensors

In the current era of "chip war" between China and the United States,the CMOS image sensor manufacturers in China are in an era of challenges and opportunities.Phase locked loop(PLL)is an essential part of image sensor.As an on-chip clock generator,PLL provides a stable clock signal for CMOS image sensor to ensure the normal operation of CMOS image sensor.The conventional clock generator is charge pump phase locked loop(CPPLL).However,the traditional CPPLL has large layout area,high power consumption and long locking time.Compared with the traditional CPPLL,the all digital phase locked loop(ADPLL)has smaller layout area,lower price and easier process migration.Moreover,ADPLL is easier to introduce fast locking algorithm,which makes ADPLL the first choice of clock generator design architecture.Although the traditional clock generator based on ADPLL has high reconfigurability and good technical scalability,compared with the solution based on CPPLL,the power consumption of the feedback path of the traditional clock generator based on ADPLL will increase.The main power consumption bottleneck is time digital converter(TDC),Because it works at a higher output frequency.The novel ADPLL architecture is applied to phase prediction and alignment of input and output clock edges through digital to time converter(DTC),which can detect phase at reference clock rate.Aiming at the problems of power consumption,jitter and locking time of traditional PLL in image sensor,this paper proposes a design method of fractional frequency division ADPLL with low power consumption,low jitter and fast locking based on counter architecture.Firstly,the dynamic adjustment lock control algorithm(DALC)is used to dynamically switch the states of ADPLL three loops through finite state machine to reduce the loop noise and shorten the locking time.Secondly,a general unit is designed to realize the integration of DTC and TDC,and the design of DTC-TDC array is realized.The controllable reset transistor is used to combine the DTC function with the TDC function using the sampling trigger.This selection can improve the gain matching between DTC and TDC,reduce the mismatch,and reduce the jitter.Finally,the clock circuit is introduced to reduce the frequency of the fractional loop,so as to reduce the power consumption of the fractional loop,simplify the design of the reset clock,and clarify the phase relationship between the reference clock and the output clock.After the overall design is completed,the back-end simulation based on 180 nm CMOS process shows that the ADPLL can realize the frequency output in the range of250MHz-2.8GHz at 1.8V supply voltage.When the locking frequency is 1.2GHz,the locking time is 1.028 ?s.When the offset carrier frequency is 1MHz,the phase noise is-102.249 d Bc/Hz.Integrating the phase noise from 1k Hz to 100 MHz,the RMS jitter is 1.7ps.