A Design Of Wideband Phase-locked Loop Circuit Applied To Array TDC

In the system of infrared single photon detection time imaging,Time-to-Digital Converter(TDC)relies on the precise clock signal to quantify the time of flight(TOF).With the continuous improvement of the range,resolution,linearity and pixel area of the TDC,it is a key point for the system of PLL-TDC to design a low jitter clock signal,which has a high precision,wide range and low bit error rate.In order to meet the requirements of infrared laser ranging imaging in special scenes such as terrain matching,the resolution and dynamic range of TDC should be able to be configured or automatically adjusted according to the depth of field,while maintaining high linearity over a wide range of measurements.This not only requires that the multiphase clock signal generated by the designed clock system be evenly phased and that the frequency or period can be selected or configured within a wide range,but also requires that the clock system be fully coupled with the TDC measurement system to ensure the clock signal serves as the cornerstone of the measurement system and can still effectively use the regulation characteristics of the generated loop to suppress the accumulation of jitter in a long-term measurement window.For this reason,a wideband phase-locked loop(PLL)circuit suitable for array TDC applications is designed.Based on this,a coupling architecture of three-level PLL-TDC with wide range,high linearity and low bit error rate is proposed.And the system use two measurement methods to reduce the inherent mismatch of the primary phase and the final phase,cutting down the system nonlinearity error.The PLL uses Auto Frequency Calibration(AFC)to cooperate with multiband voltage controlled oscillator(VCO).The 4-stage Pseudo differential delay unit are adopted to provide an eight-phase clock signal for phase resolution of the TDC.In addition,the optimal loop bandwith is adopted to suppress the output noise.And a low mismatch programmable charge pump is designe to ensure the stability of the system,which can match the variation of the frequency ratio by changing the current value.The complete pixel TDC circuit consists of a high-level 9-bit LFSR,the middle-level which is made up of 4-bit synchronous counter and the low-level 4-bit time-interpolation type TDC.With the restriction of area and power consumption of the pixel,it is important to make the middle-level and low level TDC being shared by all pixels.For the serious error problem in the multi-stage cascaded TDC,the intrinsic causes of error generation in the four typical operation steps of data latch error,carry error between segments,transmission error and false count errors are analyzed in detail.And a targeted improvement design is proposed to suppress these non-ideal factors.Based on the TSMC 0.35?m standard CMOS technology,the simulation,layout and post-simulation of the key circuit are conducted in the Cadence EDA software.The test result shows the effective locking range of the wideband PLL is from 146 MHz to 450 MHz,the RMS TIE jitter of the clock is 4ps,and the phase noise is-116dBc/Hz.When the clock frequency is locked in 250 MHz,the resolution of TDC is 500 ps,and the test results show that the DNL and INL are from-0.04 LSB to 0.04 LSB,and-0.1LSB~0.02 LSB,respectively;and when the lock frequency is raised to 450 MHz,the ultra resolution is 278 ps,and test results indicate that DNL and INL are from-0.1LS to 0.1LSB,-0.05 LSB to 0.2LSB,respectively.It can be seen that the transmission and pseudo counting bit error are eliminated and the bit error about latching and carrying are reduced effectively.In this paper,significant achievements have been made in system architecture,working mode,and circuit optimization.The successful verification of the pixel TDC can be extended to the array TDC system.