Design Of Fast Locking Charge Pump Phase-Locked Loops

The concept of phase locking was invented in the 1930s and swiftlyfound wide usage in electronics and communication. Phase locked loops(PLLs) are basic building blocks for analog and digital systems, in whichthey are used for clock and data recovery, demodulation or frequencysynthesizer applications.This paper is focused on a fast-locking phase-locked loop which cangenerate 800MHz and 640MHz reference clock used for clock generatormodule in MCU and so on. For the traditional charge pump phase-lockedloop, there is a trade-off between settling time and output phase noise.To minimize output phase jitter, the loop bandwidth should be made asnarrow as possible. However, to obtain better tracking and acquisitionproperties, the loop bandwidth should be made as wide as possible. Toachieve a fast-locking PLL while maintaining better noise bandwidth, adual-slope phase frequency detector is often used. A fast lockingphase-locked loops with a lock detector circuit is introduced. It iscomposed of a PFD for fine-tuning and a lock detector for coarse-tuning.The proposed architecture can efficiently reduce the acquisition timeof the PLL while the loop stability remains unchanged.The proposed PLL is designed in SMIC 0.1Sum CMOS technology througha 3.3V power supply. And the simulator is EldoRF of Mentor Graphics. Thesimulation results show that the settling time of the proposed PLL isbelow 1.2us. The settling time is less than the conventional PLLs. Thepower consumption is 21mW at 800MHz.In this paper, the principles of phase-locked system described andsummarized, and the structures of subcircuits are optimized. Athree-stage CMOS voltage controlled ring oscillator with differentialcontrol is given. The tuning range is about 560MHz to 1020MHz. The phase noise is -101. 2dBc/Hz at 1MHz, and the power consumption is 16.8mW.