Design Of Fast Clock Stretching Circuit And Its Application In Adaptive Voltage Scaling System

In recent years,with the continuous development of integrated circuit technology,people have increasingly higher demands on chip performance and power consumption.However,chips are affected by the fluctuation of process,voltage and temperature in the process of manufacturing and daily use.Therefore,a certain timing margin needs to be reserved in the circuit design to ensure that the chip functions well in the worst case,which results in a waste of power and performance.The adaptive voltage scaling method can effectively reduce the timing margin,while its use of frequency-division technology to correct timing error will bring additional performance loss.In light of this,the adaptive clock circuit design technology is a method of quickly fine-tuning the system frequency,which can solve the timing problem at a lower cost.A fast adaptive clock circuit design is proposed in this paper,which is applied to AVS system based on in situ error detection and correction(EDAC).It's able to fine tune the frequency quickly with the proposed adaptive clock design according to the timing information feed back by transition detector(TD),and adjust the voltage adaptively.Firstly,this paper introduces and analyzes TD and proposes two adaptive clock circuits respectively.The second adaptive clock circuit proposes a dual delay line to provide a wide operating frequency range and proposes an adaptive clock stretching/compression amount circuit to change the clock cycle properly according to the circuit timing,which improves a lot compared with the first adaptive clock.Finally,an overall system simulation and verification platform is set up to simulate and analyze the entire design.This design is implented under SMIC 28nm technology.The adaptive clock circuit has a wide operating frequency range from 61.3MHz~1.72GHz and has a smaller area cost at 840.7?m~2.It can achieve adaptive clock within the cycle.The simulation results show that the loss of system performance is reduced by7.2%~10.4%with adaptive clock design,and has improved 39.6%~42.1%compared with the frequency division/clock gating technology.For the overall AVS system design,the insertion rate of the TD is 21.39%,the area overhead is 7.71%,and the power consumption gain is 16.17%~68.44%.