Design Of A Low-jitter Multiphase Clock Generator For Array TDC

In the application of the Read Out Integrate Circuit(ROIC)system for infrared laser ranging imaging,the time-to-digital conversion of photons is performed by the system's internal single-time-to-digital converter(TDC).The digital signal post-output is further processed to measure the time of flight(TOF).As the reference signal for TDC measurement,the clock signal imposes strict requirements on its accuracy,jitter,duty cycle,phase uniformity and stability.In order to meet the ROIC system application requirements,a low-jitter multi-phase clock generation circuit has been designed.The clock architecture uses the mainstream Charge Pump Phase Locked Loop(CP-PLL)circuit.In order to meet the application requirements of the eight phase-separated clock signals of the ROIC system,the Voltage Controlled Oscillator(VCO)adopts a ring oscillator structure composed of four low-noise pseudo-difference delay units,and is matched with a double-ended output to a single-ended The shaping function of the output circuit(Double to Single Converter,DTS)obtains a multi-phase clock signal with uniform phase separation and duty ratio close to 50%.In order to obtain the optimal noise performance of the system,based on the continuous model in the s-domain,combined with the maximum phase margin method and the optimal loop bandwidth method,the loop system parameters are determined,and the high-speed,low-mismatch current rudder is used.Current Sterring Charge Pump,and detailed analysis of its noise and mismatch optimization methods to further reduce in-band noise.The second-order two-type CP-PLL has been taken as an example,introduces Zero-Order Hold(ZOH),and establishes the discrete model in the z-domain to obtain the stable boundary conditions of the system.Aiming at the noise problem of the ROIC system coupled to the PLL through the power line,the influence of the power supply noise on the phase noise of the PLL system is analyzed in detail by establishing the VCO power supply noise model,and the optimization suggestions are put forward.Based on the TSMC 0.35?m standard CMOS process,the Cadence EDA software design tool has been used to complete the circuit design,layout design and system front-end simulation verification of the PLL,and complete the MPW tape out.The actual test results show that the PLL designed in this paper is normal.When inputting a 15.625 MHz excitation signal externally,the PLL lock frequency is 250.0007 MHz,the frequency deviation is 0.7kHz,the phase difference of the rising edges of the four phase signals is 518 ps,514ps,447 ps,respectively.The duty cycle is 51.59%,and the phase noise is-114.66dBc/Hz@1MHz,rms jitter is 4.337 ps,peak-to-peak jitter is 32.2ps.In addition to the uniformity of the phase separation,the performance indicators meet the design requirements,which can meet the application needs of the array TDC.