Design Of A Low Jitter Sub-sampling Phase Locked Loop For TDC

In infrared single-photon ranging imaging applications,Time-to-Digital-Converter(TDC)as the core circuit for detecting pixels can quantify the photon time of flight(TOF)to achieve the imaging of the object under test.In order to meet the requirements of TDC for resolution and range,the output frequency of the clock generation circuit driving TDC should have the ability to continuously adjust within a certain range.To reduce the quantization error of TDC,the clock signal should also have high Stability,low jitter and low phase noise.To satisfy infrared single-photon the requirements of high-performance clocks for ranging imaging applications,this paper designs a sub-sampling phase-locked loop(SS-PLL)clock generation circuit,which has the characteristics of stable output frequency,low jitter,and wide frequency lock range.Compared with the traditional charge pump phase-locked loop(CP-PLL)clock,when the SS-PLL is locked,the sub-sampling phase detector(SS-PD)module in the SS-PLL circuit,using a low-noise complementary switch-type sample-and-hold circuit structure to realize the sampling of the high-frequency output signal by the low-frequency reference signal,converting the time difference between the reference signal transition edge and the zero-crossing position of the output signal into the output voltage difference,the output voltage difference Control the sub-sampling charge pump(SS-CP)circuit to charge and discharge the low-pass filter to realize the regulation of the SS-PLL system loop.Because the divider is not in the phase discrimination adjustment loop,the divider not only does not contribute to the output noise,but also avoids the transmission of the phase detector and charge pump noise in the traditional structure to the output terminal for amplification N~2 times.In order to meet the requirements of the TDC low-level phase subdivision,the voltage-controlled oscillator(VCO)adopts four-stage cascade structure of pseudo-differential delay unit with multi-band control,through selection the VCO frequency band and the adjustment within the frequency band realize a wide frequency range of the output signal.This article is based on TSMC 0.35?m 3.3V standard CMOS process,using Cadence tool to carry out pre-simulation,layout drawing and post-simulation verification of key units and functional modules of SS-PLL clock generation circuit and its constituent systems,and complete MPW tape,chip packaging and testing.The test results show that under the condition that the reference clock signal is 10 MHz,the SS-PLL output frequency range is 160MHz to 380 MHz,and the duty cycle is maintained at(50±2)%,the maximum rms jitter of the output clock signal is 12.0ps.At each carrier frequency,the phase noise is lower than-112d Bc/Hz@1MHz,the maximum power consumption is 42m A.Within the actual test output frequency range,the performance of the SS-PLL circuit basically meets the design specifications,but the actual test output frequency range decline and large power consumption are far from the simulation results.The SS-PLL clock generation circuit designed in this paper can meet the application requirements of array TDC.