Design And Implementation Of A Phase-locked Loop With Built-in-jitter Measurement Circuit In65nm Process

Charge-Pumped Phase-Locked Loop is widely used for microprocessor clock generationbecause of its high stability and low power consumption. With the increasing frequency ofdigital systems, the problem of uncertain clock cycle is becoming more and more serious. So, thejitter characteristic is one of the most important parameters of PLL. On chip jitter measurementcircuit, which has higher stability and accuracy, is becoming more and more popular in the fieldof clock jitter measurement. This work focus on the design of Phase-Locked Loop (PLL) withBuilt-In-Jitter Measurement (BIJM) system, which is implanted in65nm CMOS technology. Themain works of this paper are:（1）Analyzing the Mathematical model of PLL in s-domain from the view of third orderautomatic control system, the selection of loop parameter is discussed to optimize the phasenoise, and then the trade off between stability and transient character is presented.（2）Considering the impact of environmental noise on the output of Phase-Locked Loop, aseries of noise suppression techniques are used to reduce the output clock jitter at system level,circuit level and layout level respectively. Especially, a noise rejective VCO with built in activeLC filter is presented to reduce the high-frequency noise on both VC and power supply.（3）A new Vernier Delay Line (VDL) structure, whose resolution and measure range areboth tunable, is obtained by improving an existing structure.The supply voltage variationrejection design is also incorporated into the fixed and variable delay cell.（4）A novel wide range high-speed frequency divider, whose input frequency can reach ashigh as6GHz, is designed to accommodate the VDL to work a high resolution.In order to reducethe IO number, a smart circuit is designed to read out the measurement results.（5）Study the layout design techniques of mixed signal circuit.The post layout simulation shows that the whole system can achieve high power supplynoise immunity.To PLL; the output frequency can cover the range from360MHz to1.4GHz. Thepeak to peak value of long time jitter is less than5%, while the RMS value is no more than5‰.Take the typical case for example, the peak to peak value is20.107ps and the RMS value is2.157ps at600MHz.The resolution of BIJM system, whose maximum measure range is210ps,can reach as high as2ps.With four optional measure ranges, the whole system can satisfy therequirement of engineering application.