Design And Implementation Of A Phase-locked Loop With Multi-phase And Low-jitter In40nm CMOS Process

Phase-Locked Loop has been widely used as a clock generator or a synchronizer in thefield of integrated circuits. Not only the clock cycle are getting shorter, but also the timinginstability is more and more serious with the continuous improvement of the frequency of thedigital system. Therefore, the jitter property of clock signal for PLL is enforced. The multi-phasePLL, which has accuracy relationship of phase, is becoming more and more popular in SerDes.This thesis focus on the design of a PLL with multi-phase and low jitter, which is built up in40nm CMOS technology. The major research work and invention of this article have beenincluded as below:(1) Setting up the mathematical model from the basic principles of the charge pump PLL,considering the selection of loop parameters from the principle of automatic control, analyzingthe stability of the loop and dynamic performance, as well as non-ideality of multi-phase PLL,and then discussing factors of trading off in the selection of loop parameters.(2) Studying the sources of jitter and optimization strategy from external noise and internalnoise. In order to optimize the jitter of PLL, which is caused by bias voltage and supply voltagein external noise, proposed a novel technology of jitter optimization based on the bandgapreference. Designed a bandgap reference by adopting a series technical, including resistancecompensation and current compensation，which temperature coefficient is0.6ppm/℃.(3) Introducing the design of PLL with multi-phase and low-jitter in detail. A novelmulti-phase voltage-controlled oscillator was presented, through the study of VCO workingmechanism deeply, which can provide16phase outputs and adjacent phase spacing of22.5°.This paper adopts a novel differential structure by researching on the principle of the chargepump, which can eliminate the charge sharing and reduce the jitter of the PLL. Presenting atechnique of PLL which can accelerate the rate of locking, combining the pre-charging andpre-discharging of control voltage with the frequency detector, which increased the capture rangeof the PLL after loses lock and accelerated the speed of lock. Studying the lock state of PLL,proposing a detective technology of256cycles without slide, which can detect the lock state ofPLL by accurately.(4) This paper study the layout design techniques of mixed signal integrated circuits.Combining the realization of layout of PLL, discussed the factors of layout design of mixedsignal which need to be considered. Through the parasitic extraction and simulation of PLLcircuits, take the typical case, the peak to peak value of period jitter is2.22ps and the RMS valueis0.351ps at1GHz.