Design Of CMOS SAR ADC With Low Power

Recently,with ICs becoming more widely used in portable consumer electronics,modern communication systems,automotive applications and biomedical applications,the demand of its performance,power consumption and cost is increasing.As the interface between analog and data signals,Analog-to-Digital Converters(ADC)converts analog input signals to digital signal outputs,which play an important role in the development of digital electronics.This dissertation designs a low-power,medium-precision,small-sized successive approximation ADC for biomedical applications to meet the development needs of System on a Chip(SOC).The low-power successive approximation ADC depicted in this dissertation is used in glaucoma implantable intraocular pressure detection sensor,with an accuracy of 10 bit,a clock frequency of 20 kHz and the supply voltage of 1.8V.The main building blocks of this successive approximation ADC include a digital-to-analog converter(DACs),a comparator,a reference buffer,and digital control circuits.Detailed analysis of the DAC,the comparator and the reference voltage buffer is involed in shis dissertation.10-bit DAC module: This paper uses a full capacitor array charge redistribution DAC,and the use of high and low ratio of 6: 4 segmental structure.In the meantime,this paper takes full account of the matching of capacitors,analyzes the problems that should be paid attention to in layout layout in detail,and gives the method of layout optimization in order to reduce the errors introduced by the layout design as much as possible.Comparator module: A three-stage preamplifier and a dynamic latch structure are introduced,and an offset calibration technique is introduced to eliminate the offset voltage.A reasonable layout design method is also provided to ensure the realization of a high-precision comparator.Reference voltage buffer module: This paper analyzes in detail two possible reference buffer scheme,thus has chosen the structure which suits this design.In this paper,the successive approximation ADC circuit has been designed,completed the rendering and post-level simulation.The circuit adopts SMIC 0.18?m 1P6 M craft to design,its core layout area is 492?m × 541?m.Post-simulation results show that at 20 KS / s sampling rate,the effective number of bits up to 9.4 bit,power consumption of about 44.7uW.