Study Of Low-Power Charge-Redistribution Successive Approximation Register Analog-to-Digital Converter In CMOS Process

Nowadays, wearable devices, medical implant devices, wireless sensor networks and other battery-powered equipment are becoming popular, but the battery capacity has reached a bottleneck. Thus, to extend the operating lifetime of the device, the power consumption is required to be as low as possible. The analog-to-digital convertor(ADC) is the interface between the analog world and the digital world. As the core component of the device, the ADC must reduce power consumption as much as possible, too. Among various kinds of ADCs, the SAR ADC architecture is characterized by simplicity, less analog circuitry, and low power consumption. Besides, with the improved CMOS technology, power consumption continues to decrease. So SAR ADC is a better choice for low-power ADCs. Charge redistribution based SAR ADC consumes the lowest power, because it does not have static power consumption and uses the most efficient binary search algorithm, which is widely used in various fields. Therefore, the purpose of this dissertation is to study capacitor switching schemes and related circuits of the low-power charge redistribution based SAR ADC.1. Several SAR ADC core modules are analyzed, including DAC capacitor networks, sampling switches, comparators and SAR control logics. First, a detailed analysis of several typical DAC capacitor network(conventional structure, monotonic structure, VCM-based structure, tri-level structure) switching energy and linearity is performed. Then, describe two sampling switches, the conventional MOS switch and the bootstrapped switch. To be continued, three low-power comparators(the latch-only comparator, the two-stage dynamic comparator and the time-domain comparator) are introduced. Finally, three SAR control logic implementations, the static SAR control logic, semi-dynamic SAR control logic and fully dynamic SAR control logic are analyzed.2. Four DAC capacitor switching schemes are proposed, including two-level less-switch structure, multi-level structure, energy-efficient two-level structure and three-level floating capacitor structure.(1) Based on the monotonic capacitor switching scheme, the two-level switch-fewest capacitor switching scheme utilizes C-2C structured capacitor to substitute the dummy unit capacitor. Compared to the 10-bit conventional capacitor switching,its switching energy, the number of unit capacitors, and the number of switches are reduced by 90.61%, 74.7%, and 41.18%, respectively.(2) Multi-level capacitor switching scheme use 5 references(VREF, 0.75 VREF, VCM, 0.25 VREF and ground). Three references require the voltage reference generation circuit, so it is not difficult to obtain 5 references. Compared to the 10-bit conventional capacitor switching,its switching energy and the number of unit capacitors are reduced by 99.2% and 87.5%, respectively.(3) Based on the monotonic capacitor switching scheme, the energy-efficient two-level capacitor switching scheme use the reset sequence(0 1…1) instead of(1 1…1) and two C/2 in parallel rather than C. Compared to the 10-bit conventional capacitor switching,its switching energy and the number of unit capacitors are reduced by 95.31%and 74.7%, respectively.(4) The tri-level floating capacitor switching scheme uses floating capacitors to realize the capacitor switching from the least significant bit(LSB) capacitor to the most significant bit(MSB) capacitor. Compared to the 10-bit conventional capacitor switching,its switching energy and the number of unit capacitors are reduced by 99.6% and 87.21%, respectively.3. Based on 55 nm 1P7 M 2.5 V CMOS process, an 8-bit 1.0 V 1-KS/s SAR ADC was designed. Tri-level capacitor switching method is proposed, and the common-mode voltage of the DAC output is the same as that of the input signal, which does not change over the entire conversion. Compared to the conventional switching technique, its switching energy is reduced by 93.74%, and the number of unit capacitor is achieved by 74.8% reduction. To reduce leakage power, stacked CMOS pairs is introduced to implement the sampling switch. Compared to the non-stacked CMOS switch with same channel length, its leakage current is reduced by nearly half. To further reduce the power consumption, the latch-only comparator and semi-dynamic SAR control logic are used. The measurement result shows that the maximum DNL is 0.89/-0.64 LSB, and the maximum INL of 0.71/-0.97 LSB. At near to Nyquist input frequency and 1.0 V power supply, the SAR ADC consumes 7.9 n W and achieves an ENOB of 7.29-bit, resulting in a FOM is 50.5 f J/conv.-step. The ADC core occupies an active area of 160 ? 270 μm2.