High Speed And High Precision ADC Design

In recent years,the integrated circuit industry has developed rapidly.More and more functional modules are integrated into one chip,such as infrared thermal imaging sensor chip,which integrates infrared sensing,analog-to-digital conversion and digital signal processing.Among them,the device that realizes the function of analog-to-digital conversion is called Analog-to-Digital Converter(ADC),which is responsible for converting the analog electric signal reflecting infrared information into digital signal.As for the teams that develop the infrared thermal imaging sensor chip,it has far-reaching significance for the application prospect of the product and the future of the team to independently develop a high-speed and high-precision ADC,which is integrated into the chip developed by themselves.So this thesis conducted in-depth research and practice on ADC:(1)On the basis of a large number of investigations,the working principles and application characteristics of four commonly used structural ADCs are summarized.Among them,the successive approximation register(SAR)ADC has the advantages of low power consumption,simple structure,few analog circuits and easy integration,so it is the focus of this thesis.(2)As for successive approximation ADC,according to the structure of the DAC,the resistor divider structure,current superposition structure and charge redistribution structure are analyzed.And the related capacitor switching timings,such as the traditional capacitor switching timing,monotonic capacitor switching timing,energy-saving capacitor switching timing and VcM-base capacitor switching timing,are described.(3)Based on the high-speed and high-precision design requirements of ADC products,a CMOS two-stage preamplifier latch comparator is designed by using"output misalignment storage" technology,which consists of two-stage preamplifier and one-stage dynamic latch.The simulation results of Cadence show that the gain of the first stage preamplifier is 34.05 dB,-3 dB bandwidth is 88.5 MHz,the gain of the second stage preamplifier is 31.04 dB,-3 dB bandwidth is 46.6 MHz,which meets the design requirements.(4)The level conversion circuit is designed to complete the level conversion between digital circuit and analog circuit.The bandgap reference circuit is designed by "chopper modulation technology" to provide reference voltage for ADC.And the oscillator circuit is designed,whose periodic signal of a certain frequency(500KHz)is used as the clock driver of the chopper modulation circuit.(5)Based on the SMIC 0.18 ?m 1P6M 5 V CMOS process,a 16-bit 5 V 1 MS/s SAR ADC is designed.The simulation results show that under the Nyquist input condition,the effective number of ADCs in this design reaches 15.89 bits,and the SNR(Signal to Noise Ratio)is 93.99 dB,SFNR(Spurious Free Dynamic Range)is 103.95 dB.