A Research On High Speed SAR ADC Based On Time-interleaved Technique

Analog to Digital Converter(ADC)is widely used in modern information communication system.With the development of information communication technology(ICT),the demand of high speed and accuracy of analog-digital converters is increasing rapidly.Under this circumstance,analog-to-digital converters which using conventional architectures have shown some limitations.The ADC with time-interleaved can control the multi-channel parallel sub-ADCs,using digital logic,to realize the A/D conversion.The total speed of the system can be dramatically improved while ensuring the conversion precision.In current IC process,time-interleaved ADCs provide a new approach to achieve high-speed and high-precision in ADC designs.The design aims to realize a 10 bit 400MS/s multi-channel high-speed SAR ADC,based on time-interleaved.The main work focuses on two aspects: sampling time mismatch correction between multiple channels and single channel high speed SAR ADC design.In order to eliminate the mismatch of sampling time among multiple channels,based on the analysis of the causes and the principle of correction,the algorithm of averaging zero crossing is adopted.After the zero-crossing detector circuit extracts the sampling clock offset,we apply a set of delay unit to eliminate the offset.For single-channel high-speed SAR ADC design,a 10 bit 100MS/s SAR ADC with asynchronous logic is designed and the important modules in SAR ADC are studied in detail.Aiming at reducing the adverse effect of clock feed-through on sampling accuracy,an improved boot-strapped switch is adopted.An improved high-speed comparator is designed to minimize kickback noise.Meanwhile,we employ an energy-efficient switching technique to simplify circuit complexity and reduce DAC switching power consumption,as well as an redundant capacitor structure for correction of comparator offsets.After that,the determination of the unit capacitance is discussed.In the overall layout of the system,the symmetry and matching of the DAC capacitor array are considered,as well as analog circuit.The negative influence of parasitic parameters,introduced in the layout,on the system performance is reduced.The design succeeds in realizing a multi-channel high-speed SAR ADC circuit based on time-interleaved technology,based on the TSMC 90 nm CMOS process,with integral layout design and simulation verification.The overall chip core area is 700 × 730.The post-simulation results show that the single-channel SAR ADC has an SNR of 61.02 dB,ENOB of 9.84 bit,SFDR of 70.75 dB and Fo M of 24.1p J/ conv.-step at a sampling rate of100MS/s with 2.033 m W power consumption.Single-channel SAR ADC layout simulation result: SNR is 59.93 dB,ENOB is 9.72 bit,SFDR is 69.36 dB.When the input signal frequency is 35.123 MHz and the sampling rate is 400MS/s,the overall four-channel time-interleaved high-speed SAR ADC has an SNR of 58.23 dB,ENOB of 9.38 bit,SFDR of 68.76 dB and Fo M of 32.6pJ/conv.-step with an overall power consumption of 8.691 mW.The overall four-channel time-interleaved high-speed SAR ADC layout simulation result:SNR is 57.13 dB,ENOB is 9.19 bit,SFDR is 68.18 dB.