Design Of A 12-bit Successive Approximation Analog-to-Digital Converter

Today,with the rapid development of the integrated circuit industry,more and more products come into the various industries of our lives,bringing sufficient opportunities as well as more challenges.In the integrated circuit industry,digital integrated circuits have developed especially rapidly in recent years and gradually become the mainstream.However,many signals in life are analog signals,so there is more and more demand for analog-to-digital converter as the interface between the digital world and the analog world.With the continuous development of CMOS technology,SAR ADC has made great progress in speed and accuracy,and has been widely used in various fields.In this paper,the performance parameters,basic structure and working principle of SAR ADC are introduced in detail,and several main modules in the structure are analyzed.The design goal of this paper is a 12-bit 30MS/s SAR ADC.In the design,the core of the comparator module uses the improved dynamic preamplifier module and dynamic latch,the two modules do not have any static voltage or static current,so they have very low power consumption.In addition,the output offset calibration structure is used to calibrate the offset voltage.The DAC module adopts a two-stage segmented capacitor structure,which effectively reduces the area of the capacitor array,and adopts a fully differential capacitor array structure to suppress noise interference according to its symmetry.The core of the logic module is the true single-phase clock circuit.Its main function is to complete the frequency division of the signal.And then based on this core we complete the design of the logic module.The overall circuit structure is simple and has low power consumption.In addition,in order to optimize the overall performance,bootstrap switch and ESD protection circuit are also used.In this paper,the design of SAR ADC is completed under the supply voltage of 3.3V.The circuit is simulated by cadence virtuoso software.The simulation results show that under the sampling frequency of 30 MHz,the spurious-free dynamic range is 80.4d B,the signal-to-noise distortion ratio is 72.2d B,and the effective number of bits is 11.7 under the sampling frequency of 7.2MHz.Finally,the layout design is completed based on the 180 nm process of TSMC.