Design Of High-Precision Successive Approximation Analog-to-digital Converter

This paper using CMOS process realize a successive approximation analog to digital converter(ADCs)with low power consumption,small size,easy to implement multiplexing features.Although its conversion accuracy and conversion speed is at a medium level,but it meet the current needs of portable electronics,instrumentation,industrial control and other aspects of the signal acquisition,which makes this SAR ADC widely used.The low power SAR ADC designed in this paper use 1.8V supply voltage,has 12 bit precision and 2Mbps speed.The design use capacitance mismatch calibration technology,has low-power,high-precision characteristics.The work of this paper is divided into three parts:(1)Designed a segmented and deferential capacitive DAC(MDAC)with high 6 bit and low 6 bit.This segmented and deferential MDAC design significantly reduce the chip area and dynamic power.(2)Research multi-capacitor array mismatch and design the calibration capacitor array(CDAC).This CDAC can effectively correct capacitance mismatch and comparator offset,meet the design requirements for accuracy.(3)Design the control logic and use Verilog implement the MDAC and CDAC control circuit.This control logic first calibrate the MDAC from MSB to LSB,then calculate and store the calibration code,at last put the calibration code on the CDAC and get the final output of MDAC serial conversion results.This design use Verilog-HDL description,design compliler comprehensive,IC Compliler layout,and analog-digital co-simulation,finally meet the design requirements.On the basis of complete ADC circuit design simulation,this paper also completed the physical layout of the circuit,after.The successive approximation ADC using SMIC 0.18 um CMOS manufacturing technology,the chip area is 700 um ×750um.Under 2.02 Mbps the measured results show that its SNDR is 71.55 dB,its SFDR is 91.82 dB,its ENOB is 11.59,power consumption is 1.06 mW.