Research And Design Of CMOS High Speed Lowphase Noise Phase-Locked Loop Circuit

With the progress of communication technology and semiconductor technology,some key modules such as analog-to-digital converter and serial interface,which need clock signal as driver,have higher working frequency in on-chip system.This paper focuses on the application of PLL in on-chip clock generation circuit which requires low phase noise and low jitter.Firstly,the paper analyzes the working process of PLL and conducts modeling analysis to understand the loop characteristics of PLL.Then the realization of each module circuit and the analysis of non-ideal factors are discussed.Then the model is used to analyze the effect of loop bandwidth on phase noise of PLL and to select the appropriate bandwidth to ensure the lower jitter performance.In addition to selecting the right loop bandwidth,at the system level with more advanced phase-locked loop architecture can obtain the phase noise of more excellent properties,such as ultra broadband phase-locked loop can greatly increase the bandwidth to suppress the contribution of VCO phase noise and Sub-Sampling PLL can greatly restrain the in-band noise of charge pump.And the technique of injection locking can reduce the phase noise of VCO.In this paper,advanced Sub-Sampling PLL architecture is adopted to complete the PLL circuit design,which can be divided into under-sampling loop and lock-frequency loop.Only the Sub-Sampling phase detector is responsible for the phase detection function when the phase lock loop is locked,and the Sub-Sampling loop works normally.However,the phase detector of the frequency lock loop has a phase detection dead zone,and the auxiliary phase lock loop locks to the desired frequency.Firstly,the Sub-Sampling phase detector,Sub-Sampling charge pump and voltage-controlled ring oscillator are designed.Then the appropriate loop bandwidth is calculated according to the results of noise simulation,and the loop filter parameters are obtained.Verilog-A is used to verify the correctness of the selected loop parameters.After that,the design of the phase-locked loop circuit is completed,the traditional phase-locked detector with phase-locked dead zone is improved,and a kind of reference voltage generating circuit is designed to adjust the delay of the phase-locked loop delay circuit through digital method.Under the condition of fully considering the matching of devices and the isolation of noise,the layout and wiring of the Sub-Sampling PLL are carried out and the post-simulation verification of the circuit is completed.Under the 40nm CMOS process,the final simulation results show that the output frequency range of PLL is 1.7?3.05 GHz.When the output frequency of the PLL is 2.5 GHz,the locking time is 3.2?s and the power consumption is 27.3mW.The phase noise at the 1MHz frequency offset of the PLL is calculated to be-111.4dBc/Hz,the jitter in the integral range of[1K,100M]is 436.5fs,the FoM value of the phase noise and power consumption is 165dB,and the FoM value of the jitter and power consumption is-232.8dB.