Research And Design Of Low-noise And Low-spur Sub-Sampling Phase Locked Loop

Wireless transmission systems have been widely used in people’s daily life,and digital-to-analog/analog-to-digital converters are bridges connecting the digital world and the analog world.The phase-locked loop synthesizer not only has the characteristics of short frequency change time and wide adjustment range,but also has the advantages of high output signal accuracy and low noise,and is an indispensable module for providing clock signals for digital-to-analog/analog-to-digital converters in wireless transmission systems.With the rise of the Internet and the huge consumption of electronics,a low-noise,low-spur subsampling phase-locked loop is designed to meet the needs of phase-locked loops in low-frequency SOC system applications.The traditional Charge Pump Phase-Locked Loop(CPPLL)can provide clock signals,but there are problems such as in-band noise,spur and other poor indicators.Traditional Subsampling Phase-Locked Loops have low in-band noise,but they also have the problem of output spur.Therefore,improving the phase-locked loop phase noise and spur performance has always been the focus of research.(1)In view of the design requirements of low spur,a low-mismatch Sub-sampling Phase Charge Pump(SSCP)is designed,and complementary switching technology is used in the structure to reduce the switching delay caused by different types of MOS switch transistors to avoid the clock feed-through effect.A programmable current regulation network fine-tunes the charge pump current to achieve optimal current matching based on the application.A unity gain amplifier that clamped the SSCP output voltage is designed,stabilized the Voltage Controlled Oscillator(VCO)bias voltage(V_C)and reduced the SSCP quiescent current mismatch rate to less than 1%.Also a unity gain amplifier is added which reduced the impact of charge sharing and charge injection,and reduces the subsampling phase-locked loop output clock spur.(2)In view of the design requirements of phase noise,low noise Sub-Sampling Phase Detector(SSPD)is designed.And the transmission gate switch is used to increase the sampling range and reduce the sampling distortion.Differential isolation buffers buffer spur and isolate noise crosstalk effects from the front and rear paths.A resistor-programmable toroidal voltage controlled oscillator(Ring VCO)with regulator bias is designed to have high output clock accuracy,low noise,and good module linearity.The programmable resistor regulation network uses feedback technology to reduce the effect of voltage fluctuation on the voltage-controlled oscillator,realizing the high-stability output of the voltage-controlled oscillator and avoiding the deterioration of loop phase noise.(3)The circuit design is simulated and verified in the SMIC 110nm CMOS process environment.Simulation results show that the power dissipation during loop stabilization is 1.85mW at 1.2V supply voltage.When the SSCP charge-discharge current is 22u A,the quiescent current mismatch rate is less than 1%.After Pss+Pnoise simulation in Spectre,the noise fitting of each circuit module is performed by Matlab and then the overall phase noise of the subsampled phase-locked loop is obtained.The in-band noise is-118.6dBc/Hz at the carrier offset of 100KHz.After the loop output clock signal stabilizes at 64MHz,Fourier the output clock signal to obtain a spur which are less than -89dB.