Design And Implementation Of MIPI DSI Controller

With the development of mobile Internet,mobile phones and other multimedia devices have been widely popularized.The requirements of mobile devices for high-definition image acquisition and display technology have been further enhanced.Consumers increasingly favor mobile devices with long battery life,large display size and high-definition resolution.Issues such as power consumption,performance,time,and overall system cost have brought new challenges to the mobile device industry.To this end,the MIPI Alliance proposes a new display serial interface protocol DSI(Display Serial Interface),which pr ovides a high-speed serial interface between the host processor and the display device.The DSI interface has lots of advantages including low power consumption,high bandwidth,low electrical measuring instrument(EMI).This thesis focuses on the design of MIPI DSI controller.The DSI controller includes three parts:application layer,low level protocol layer and lane management layer.The controller supports command mode and video mode.What's more,it supports RGB888 and RGB565 data formats.It can support up to four data channels and has two-way communication function.The design of this thesis focuses on forward transmission and reverse reception.During the design process,a modular design scheme is used to divide each layer into different functional modules.The design methods of DPI,DBI interface and APB bus are introduced in detail.In order to ensure the correctn ess of the data transmission,two check mechanisms of ECC and CRC are added to the design process,and the design process of the data packet encoding module and decoding module is given.The state machine of the relevant module adopts three-stage encoding design.The RTL code in this thesis is designed in Verilog HDL language.And the module design and simulation verification are carried ou t under Linux system.The tools used are vcs and verdi of synopsys.After simulation verification,the function of each module in this design meets the design requirements.The design uses the SMIC40nm process,the circuit area is 49686?m~2,and the power consumption is 15.1mw.