Research And Design Of Display Interface Receiver Based On MIPI Protocol

With the rise of various voice and video instant messaging methods,large screens,high pixels,and portability have become the mainstream trends in the development of mobile handheld terminals.Especially the emergence of wearable devices has put forward higher requirements for data transmission speed,power consumption and interface integration.In order to reduce the complexity of communication between different modules and make it easy to integrate and standardize,manufacturers have developed various standard protocols.Among them,the Mobile Industrial Processor Interface(MIPI)standard is widely used in mobile handheld terminal display applications due to its complete technology and strong applicability,so it has extremely high research value.This article takes MIPI D-PHY and MIPI DSI as the starting point,and designs a display interface receiver circuit based on MIPI protocol.The main work of this paper is:after a brief introduction of MIPI D-PHY and MIPI DSI,the design indicators and design points of the high-speed receiver module and low-power receiver module in the display interface receiving circuit are analyzed,and the key circuit of the physical layer is completed.(Including high-speed receiving module and low-power receiving module)circuit design,layout design and simulation verification.In the design of the high-speed receiving module,the high-speed comparator is calibrated by current injection,thereby reducing the data crosstalk in the high-speed data transmission process and increasing the data transmission rate.In the design of the low-power receiving module,a circuit structure with hysteresis function is adopted,which improves the anti-interference ability of the circuit,and plays a vital role in suppressing and filtering noise,burrs,and high-frequency interference.In the single-channel design,considering that most of the power consumption of the entire circuit is mainly from the high-speed receiving module,in order to effectively reduce unnecessary power consumption,each module is equipped with an enable port to support the channel management layer according to the data transmission volume.Optimize the configuration of the number of channels and support on-demand switching between high-speed receiving mode,low-power receiving mode and ultra-low power mode.At the same time,in order to reduce the complexity of the circuit,the same circuit design is adopted for the five channels.The simulation results show that the single channel of the MIPI interface receiver circuit designed in this paper consumes 22.86?W in ultra-low power consumption mode,and its data transmission rate can reach 20 Mbps and power consumption is 236.5?W in low power receiving mode.In the high-speed receiving mode,the data transmission rate can reach 1.5 Gbps,the power consumption is 11.5m W,and when the four channels are working at the same time,the data transmission rate can reach 6 Gbps.After the layout design is completed based on SMIC's 180nm process,the overall layout area of the analog part including I/O is 1788*615?m~2.