A Low-power MIPI Interface Is Designed For Display Devices

As an important transmission medium of people and information,display devices has changed from single to multiple.Display devices became large-sized,high-resolution and colorful.In order to match new display devices,the requirements for interface performance are gradually increased.The MIPI(Mobile Industry Processor Interface)interface has become a hotspot for extensive research with lower power consumption,higher data transmission rates and multiple working mode capabilities.This thesis is based on the research and design of a high-resolution AMOLED display panel to design a low-power MIPI interface circuit for display devices.The overall circuit architecture includes low-power transmission,low-power receiving,power supply and high-speed receiving module.The low-power transmitter uses an asymmetric current source array controlled by digital signals at the push-pull input to charge the RC structure to reduce the input signal slew rate.Connecting the multi-impedance branch at the output of the push-pull structure and adjust the signal slew rate at the output.Low-power receiving module uses hysteretic comparator structure to reduce noise sensitivity of received signal.In addition,the MIPI low-speed clock oscillator module was further designed for clock reference in low-power modes.Finally,the overall MIPI chip design is completed based on UMC 80 nm CMOS process,the chip area is 4917um*631.4um.The post-simulation results show that the maximum power consumption of the low-power transmission analog power supply is 4.33 m W and the maximum power consumption of the digital power supply is 50.99 u W.In standard mode,the maximum output slew rate is 369.9mv/ns with 0-70 pf.Low power receiving VIH=737 mv,VIL=693mv,hysteresis range is 48 mv.MIPI circuit modules can work normally to meet the design requirements.