The Research And Design Of MIPI D-PHY Display Interface Of Transmitter

Mobile Industry Processor Interface(MIPI)is an open standard for Mobile application processors.The MIPI D-PHY reduces time-to-market and design costs for mobile devices through standardized interfaces,meets richer requirements for high bit rates,and improves device compatibility by simplifying integration of built-in components for mobile devices with its unique extensibility feature.Based on MIPI D-PHY protocol,this paper studies and completes the design of an interface circuit applied to the display device at the sending end,which includes three important modules,such as bias circuit,low-power sending circuit and high-speed sending circuit.1.In the bias circuit,it includes a reference voltage module that provides a stable voltage for the sending circuit,a bias current module that provides a stable current for the sending circuit and an impedance correction module that regulates the internal and external impedance of the circuit.In order to improve the output precision,a band-gap reference source based on chopper modulation technology and fine tuning technology is adopted to reduce the influence of offset voltage and transistor mismatch on the reference voltage,and the overall precision is increased by 88 times.2.the sending circuit,low power consumption,using the method of control the bias current and impedance correction was adjusted the adjustment of the rate of output swing,the sending circuit level and low power consumption mode conversion problem,puts forward a negative feedback loop structure,to ensure that the power supply voltage of 1.8V,the drive to achieve stable and controllable high level 1.2V output.3.In the high-speed sending terminal circuit,including serializer circuit,single-terminal to differential circuit,current mode drive circuit.In order to improve the transmission rate of serial data,a fully differential circuit based on sensitive amplifier is used to realize the trigger.Single-ended to differential circuit is to convert the single-ended signal into a differential form for transmission.Compared with single-ended transmission,differential transmission has good anti-interference and noise suppression ability.The current mode driving circuit is used to improve the overall driving ability of the circuit.In order to reduce the design complexity,save area and power consumption while ensuring the noise suppression ability and signal integrity,a two-level cascade current mode driving circuit structure is adopted.In this paper,based on SMIC 0.18?m CMOS process,the circuit and layout design are completed and the simulation analysis is carried out.Finally,the flow sheet is completed.The whole chip area(including analog and digital parts)is1788?m×2877?m.The simulation results show that the maximum power consumption of low power transmission circuit is 477?W,the single channel adopts low speed data transmission of 20 Mbps,and the highest transmission rate of the high speed transmission circuit is 1.5Gbps,all of which meet the design requirements.