Back-end Design Of GPU Core Computing Unit Based On 7nm Technology

With the process feature size of integrated circuit entering the deep nanometer stage,the chip scale is increasing,and the back-end design is becoming more and more complex.The increasing crosstalk and multi-mode and multi-terminal angle increase the difficulty of timing convergence,and the increase of interconnection complexity aggravates the degree of winding congestion and manufacturability of the chip,and the problem of power consumption becomes more and more important.Therefore,it has certain application value to carry out the research work of back-end design under the new process.This project is originated from an enterprise project.It is planned to complete the back-end design of a GPU core computing unit based on 7Nm technology.The achievements of this paper are as follows:1)Complete the layout and wiring of GPU computing unit under 7Nm process conditions,including layout planning,layout planning,clock tree synthesis and wiring.In the layout planning stage,based on the new physical design rules of 7Nm process,the placement of macro cells is determined according to the data flow between different modules,and the power planning and physical cell insertion are carried out at the same time.In the layout planning stage,the placement of standard cells is completed through the layout target estimation,and the unreasonable distribution of winding resources is solved by the reorganization of scanning chain,and the timing is adjusted In the phase of clock tree synthesis,the common clock tree structure and performance evaluation parameters are studied,the synthesis of clock tree is implemented,and the timing violation problem is solved by using the method of advance skew;in the phase of routing,the global routing,track allocation and detailed routing are used to complete the routing work,while the crosstalk analysis and manufacturability design are carried out.2)Using SPG(Synopsys physical guidance)technology to optimize the back-end design.In view of the poor timing matching between logic synthesis and layout and routing stage,DCG synthesis is used.DCG combines layout information in layout and routing to enhance post placement delay optimization,providing better start-up network table for back-end design.In icc2 tool layout,DCG placement information is used as the starting point for optimization,speeding up timing convergence.SPG supports congestion optimization,improving windability At the same time,aiming at the problem of power consumption,the gate clock unit is inserted and the multi bit merging is created in the DCG synthesis.3)Enter the eco phase to fix the remaining violations.Different types of violations were analyzed,and corresponding repair methods were used to repair DRV violations,DRC violations,establishment time violations and retention time violations.The final design results show that the maximum frequency of GPU core computing unit module designed in this study can reach 2.3ghz,the size is 535.8000 ? m × 590.6400 ? m,the scale can reach 1.3 million gates and the time sequence convergence,there is no violation of design regularity.Through formal verification,it can reach the final actual project signing standard,and it can deliver flow chips.Through the research of this project,it provides a new solution to the timing and congestion problems faced by the back-end design of deep nano process nodes,and provides some reference opinions for the development of the related integrated circuit back-end design.