Deep Sub-micron High-performance Digital Asic Chip Back-end Design

In this dissertation, we make a deep research on the key technology in ASIC backend design,such as Logic Synthesis, Static Timing Analysis, Power Distribution Network Analysis and Design, Clock Tree Design and Synthesis, Floorplan and Routing. Based on the key technology, we propose lots of new design thinking and finish the backend work well and then send the GDSII file of the chip to SMIC .Ltd.Corp for fabrication.The main works can be summarized as follows:1. Logic Synthesis in high performance sub-micron ASIC design and the Logic Synthesis process of Radar digital signal processing SoC chip,2. Static Timing Analysis in high performance sub-micron ASIC design and the Static Timing Analysis process of Radar digital signal processing SoC chip ,3. Power Distribution Network Analysis and Design in high performance sub-micron ASIC design and the Power Distribution Network Analysis and Design of Radar digital signal processing SoC chip,4. Clock Tree Design and Synthesis in high performance sub-micron ASIC design and the Clock Tree Design and Synthesis of Radar digital signal processing SoC chip,5. Floorplan and Routing in high performance sub-micron ASIC design and the Floorplan and Routing of Radar digital signal processing SoC chip...