Implementation Of AVS Video Decoder

The implementation flow of ASIC design includes logic synthesis and physical design, which are very important steps in the whole flow for IC design. It not only decides function of ASIC, but also affects performance, cost and power at a large degree. In deep submicron technology below 0.18um, as the ratio of interconnect delay and power density all raise dramatically, timing closure and power optimization become the most important problem for physical design.The main tasks for ASIC implementation are logic synthesis and layout, this paper focus on logic synthesis flow based on DC, P&R flow using IC Compiler, formal verification flow using Formality and post_layout static timing analysis flow based on Primetime. Firstly, we introduced the logic synthesis tool Design compiler, physical design tool IC compiler, static timing analysis tool Primetime and logic equivalence check tool Formality. Then we summed up the main delay models, parameter extraction and timing optimization. Thirdly, we built the synthesis and physical implementation flow of the AVS chip based on TSMC 0.13um process. The synthesis flow translates RTL code to gate level netlist, physical design mainly focus on design planning, placement, clock tree synthesis, routing and dfm related operation, static timing analysis and formal verification are used to gurantee timing closure and logic equivalence during translation. Then we give the timing reports and logic check reports during the flow, the reports implied that the timing is closure and logic translation is correct. Finally, the summary and outlook of the whole research are given.