The Design Of The Digital Part Of Image Sensor Based On LVDS

As the development of digital technology, semiconductor technology and network, the digital products integrated with video,audio,communication are popular. And the speed of the development changes with each passing day. Just a few years, the pixels of digital cameras change from hundreds of thousands to several mega. Therefore, the important of the camera is the image sensor which is rapid, in particular CMOS image sensor. Because of low power, high reliability and small size, CMOS image sensors develop rapid, and have development potential.The speed of CMOS image sensor's data out is slow, which affect its application serious. So the purpose of this research is to solve the problem and design the digital system of a image sensor chip—SP230A. The main task of this article is to design the digital system of the high speed image sensor, synthesize and route. In the design process, three major problems solved. The first problem is the parallel data into high-speed serial data at the high clock frequencies. The second is setup time violation in synthesis process. The third is clock tree synthesis. And through the rational design and optimization, placement and routing is completed in a limited space. The results of the test confirmed that chip design fully meet the targets.First of all, this dissertation introduces the background and the feasibility of the design. It introduces the design idea and the design method of SP230A. And the structure and characteristic of SP230A is introduced. Secondly, the scripts of Design Compiler is designed, the result of Design compiler is analyzed. I was solved the setup time violation of design and optimized timing. P&R(placement and routing) is the main task of IC physical design. Astro and SOC Encounter is compared the advantages and disadvantages. According to design needs, SOC Encounter is chose the tool of the physical design. Timing closure is the main issue in deep submicron. The traditional clock trees can't satisfy the request of the design. So the thesis introduces the hierarchical clock trees design and answers the question of timing closure. The main issue is to design power distribution and overcome IR drop and EM effect. The author analyzed static timing and solved the hold time violation. Finally, physical design verification checks the design rule of layout. The antenna effect is eliminated and the route of illegitimate is avoided. After the chip taped out, the result of the test is satisfied the original design.